National Semiconductor Corporation

Joseph Douglas Wert

Richard L Duncan

Angela H Wang

Timothy Don Davis

Dan E Daugherty

William E Ballachino

A system and method are disclosed for providing an integrated circuit low voltage thin gate input/output structure with thick gate overvoltage/backdrive protection. In an advantageous embodiment of the present invention, a transfer gate of the input/output structure comprises at least one thick gate native (or depletion) n-channel metal oxide semiconductor (NMOS) transistor that is connected to an output pad node of the input/output structure. The thick gate native (or depletion) NMOS transistor prevents current from the output pad node from entering the input/output structure when a voltage level of the output pad node is high.

System and method for providing a low voltage thin gate input/output structure with thick gate overvoltage/backdrive protection

A floating CMOS input circuit is disclosed that does not draw direct current. The floating CMOS input circuit comprises a first inverter circuit that is capable of being coupled to an input voltage (Vin) and an n-channel pull-down transistor (N) that is coupled to the first inverter circuit. The n-channel pull-down transistor (N) pulls the input voltage (Vin) on the first inverter circuit to a hard ground when the input voltage (Vin) is not driven high. This eliminates the leakage of direct current in the first inverter circuit. The floating CMOS input circuit also powers up in a known state.

Floating CMOS input circuit that does not draw DC current

A level shifter for use in a dual power supply circuit operating from a VDD power supply and a VDDH power supply greater than the VDD power supply. The level shifter indicates to a status circuit in the VDDH power supply domain that the VDD power supply is enabled. The level shifter detects when the VDD power supply is on and sets an enable signal to the status circuit. The level shifter also detects when the VDD power supply is off and clears the enable signal to the status circuit.

Apparatus and method for level shifting in power-on reset circuitry in dual power supply domains

A circuit includes a first native or depletion n-channel Metal Oxide Semiconductor (MOS) transistor and a second native or depletion n-channel MOS transistor. The first and second native or depletion n-channel MOS transistors are capable of receiving an input signal. The circuit also includes a standard p-channel MOS transistor and a standard n-channel MOS transistor. The standard MOS transistors are coupled to the native or depletion n-channel MOS transistors and are capable of providing an output signal. The output signal is based on the input signal. Gates of the native or depletion n-channel MOS transistors may be thicker than gates of the standard MOS transistors. The native or depletion n-channel MOS transistors may be capable of blocking excessive voltage from the standard MOS transistors. The standard MOS transistors may be capable of selectively blocking the input signal from the output signal.

Transfer gate having overvoltage protection and method

A logic gate for use in an electronic system comprising: i) a first component operating from a low voltage power supply rail; ii) a second component operating from a high voltage power supply rail; and iii) an over-voltage protection circuit that detects an over-voltage on an output pad of the first component and, in response to the detection generates from the over-voltage a generated power supply voltage and a generated reference signal. According to an advantageous embodiment of the present invention, the logic gate comprises a plurality of transistors, wherein the plurality of transistors are powered by the generated power-supply voltage and at least one of the plurality of transistors is turned ON and OFF by the generated reference signal.

Circuitry for providing overvoltage backdrive protection

A variable drive strength hysteresis input circuit is disclosed that comprises pull-up circuitry and pull-down circuitry. A variable drive strength circuit changes the pull-up drive strength and the pull-down drive strength in response to receiving an input voltage signal that transitions either from a low level to a high level or from a high level to a low level. In one advantageous embodiment the variable drive strength hysteresis input circuit comprises four p-channel MOSFET transistors and four n-channel MOSFET transistors. The invention efficiently reduces transition noise in the inputs to an integrated circuit chip.

Variable drive strength hysteresis input circuitry

A latch for detecting a state transition of an input signal and generating a self-clearing reset signal on an output. The latch comprises: 1) a transfer gate for passing the input signal to a first node when the input transfer gate is enabled; 2) a transition detector for detecting a transition of the first node from a first to a second state, wherein the transition detector, in response to the transition, disables the transfer gate and enables the reset signal; and 3) a feedback loop circuit for detecting enabling of the reset signal. The feedback loop circuit, in response to the enabling, changes the first node from the second state back to the first state. The transition detector, in response to the changing of the first node back to the first state, disables the reset signal.

Short circuit protection apparatus with self-clocking self-clearing latch

A logic gate for use in an electronic system comprising: i) a first component operating from a low voltage power supply rail; ii) a second component operating from a high voltage power supply rail; and iii) an over-voltage protection circuit that detects an over-voltage on an output pad of the first component and, in response to the detection generates from the over-voltage a generated power supply voltage and a generated reference signal. According to an advantageous embodiment of the present invention, the logic gate comprises a plurality of transistors, wherein the plurality of transistors are powered by the generated power supply voltage and at least one of the plurality of transistors is turned ON and OFF by the generated reference signal.

A power monitor circuit for notifying processing circuits operating from a first power supply (VDD) that a second power supply (VDDIO) is powered up. VDDIO is greater than VDD. The power monitor circuit comprises: 1) a voltage divider circuit coupled between the second power supply and ground having an output node that goes high when the second power supply is powered up; and 2) an odd number of serially connected inverters operating from the first power supply. An input of a first serially connected inverter is connected to the voltage divider circuit output node. An output of the last serially connected inverter produces a status signal that is the inverse of the voltage divider circuit output node. The status signal is an input to the voltage divider circuit that minimizes the voltage divider circuit&#x2014;s current consumption when the second power supply is ON, while maintaining the status signal value.

Power-up detection circuit with low current draw for dual power supply circuits

An extended voltage range level shifter is provided that includes an input inverter and first and second circuit branches. The input inverter includes thin-gate devices, is coupled to an internal power supply, and is operable to receive internal data and to generate inverted internal data. The first circuit branch includes a p-type, thick-gate transistor that has a source coupled to an external power supply; a first n-type, thick-gate transistor that has a drain coupled to a drain of the p-type transistor and a gate operable to receive a reference voltage that is less than the external power supply and greater than the internal power supply; and a second n-type, thin-gate transistor that has a source coupled to ground, a drain coupled to a source of the first n-type transistor, and a gate operable to receive the internal data. The second circuit branch also includes a p-type, thick-gate transistor that has a source coupled to the external power supply, a drain coupled to a gate of the p-type transistor for the first circuit branch, and a gate coupled to the drain of the p-type transistor for the first circuit branch; a first n-type, thick-gate transistor that has a drain coupled to a drain of the p-type transistor and a gate operable to receive the reference voltage; and a second n-type, thin-gate transistor that has a source coupled to ground, a drain coupled to a source of the first n-type transistor, and a gate operable to receive the inverted internal data.

Extended voltage range level shifter

A double translation voltage level shifter is provided that includes a first translator comprising thin-gate devices and a second translator comprising thick-gate devices. The first translator is operable to receive an internal power supply voltage associated with an internal voltage domain, to receive a transitional power supply voltage associated with a transitional voltage domain, and to receive internal data. The internal data comprises data in the internal voltage domain. The first translator is also operable to generate transitional data based on the internal data, the internal power supply voltage, and the transitional power supply voltage. The transitional data comprises data in the transitional voltage domain. The second translator is operable to receive an external power supply voltage associated with an external voltage domain. The second translator is also operable to generate external data based on the transitional data and the external power supply voltage. The external data comprises data in the external voltage domain.

Double translation voltage level shifter and method

For use in an integrated circuit interface to a memory device, there is disclosed an input circuit having an input interface that is capable of receiving one of a high speed, high power signal and a low speed, low power signal. The input circuit of the present invention is capable of preventing direct current leakage within the input circuit when the input circuit is operating in a low speed, low power mode. The input circuit of the present invention comprises a multiplexer that is capable of receiving both high speed, high power signals and low speed, low power signals. The input circuit of the present invention also comprises a switch that is capable of preventing a high speed, high power signal from causing direct current leakage within the input circuit when the input circuit is operating in a low speed, low power mode.

Dual purpose low power input circuit for a memory device interface

A system for generating a reference voltage is provided that includes a first p-type, thick-gate transistor, a second p-type, thick-gate transistor, a third p-type, thick-gate transistor, and a fourth p-type, thick-gate transistor. The first p-type transistor has a source that is coupled to an external power supply, a gate, and a drain that is coupled to the gate. The second p-type transistor has a source that is coupled to the drain of the first p-type transistor, a gate, and a drain that is coupled to the gate. The third p-type transistor has a source that is coupled to the drain of the second p-type transistor, a gate that is operable to receive a mode indicator, and a drain that is coupled to ground. The fourth p-type transistor has a source that is coupled to the drain of the second p-type transistor, a gate that is operable to receive an inverted mode indicator, and a drain that is coupled to ground.

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Arlington, TX, United States of America

Joseph Douglas Wert