Cadence Design Systems, Inc.

Joseph Dexter Smedley

Brett Allen Neal

Richard Allen Woodward, Jr

Randall Scott Lawson

Sean Bergan

Jelena Radumilo-Franklin

Frank X Farmar

Paul S Musto

Gregory M Horlick

Charles Winston Grant

Abhay K Agarwal

Stephen Ralph Russo

The present disclosure relates to a computer-implemented method for electronic design simulation. The method may include providing, at an electronic design associated with one or more computing devices, a differential pair between a driver and a receiver. The method may further include identifying one or more segments associated with the differential pair and automatically solving, using the one or more computing devices, for a dynamic phase associated with the one or more segments.

System, method, and computer program product for static and dynamic phase matching in an electronic circuit design

The present disclosure relates to a method for visualizing an electronic circuit design. The method may include receiving the electronic circuit design, wherein the electronic circuit design includes at least one timing constraint. The method may also include identifying the at least one timing constraint and displaying, at a graphical user interface associated with the one or more computing devices, the at least one timing constraint and a physical routing associated with the electronic circuit design. The method may further include receiving a user input associated with the electronic circuit design and dynamically updating a graphical representation of the at least one timing constraint, in response to the received user input.

Display process

A system and method are provided for establishing an automated routing environment in an electronic design automation (EDA) work flow for the routing of a circuit design. A user may merely specify a flow via pattern, a flow via location, and a start and end terminal and thereby, the auto router or path finder will automatically find the least-cost paths between each of the start terminals through at least one intermediate via of the flow via and ending at an end terminal. Upon successful routing of all needed terminals, an at least partially routed circuit design may be output.

Method and system for routing optimally between terminals through intermediate vias in a circuit design

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Chelmsford, MA, United States of America

Joseph Dexter Smedley