Lucent Technologies Inc.

Qlogic Corporation

Silverstorm Technologies, Inc.

Joseph David Coyne

Todd M Rimmer

Duane J McCrory

Bijit Thakorbhai Patel

Todd Matters

William P Jordan

Michael Shinkarovsky

Clifford B Cole

A shared I/O subsystem for a plurality of computer systems where a plurality of virtual I/O interfaces are communicatively coupled to the computer systems. Each of the computer systems includes a virtual adapter that communicates with one of the virtual I/O interfaces. The shared I/O subsystem also includes a plurality of I/O interfaces and a forwarding function. The forwarding function includes a plurality of forwarding table entries that logically arrange the shared I/O subsystem into one or more logical switches. Each of the logical switches communicatively couples one or more of the virtual I/O interfaces to one of the I/O interfaces. A logical switch receives a first I/O packet from one of the virtual I/O interfaces and directs the first I/O packet to at least one of the I/O interface and one or more of other ones of the virtual I/O interfaces. A logical switch also receives a second I/O packet from the I/O interface and directs the second I/O packet to one or more of the virtual I/O interfaces.

System and method for implementing logical switches in a network system

A shared I/O subsystem for a plurality of computer systems. The shared I/O subsystem includes a plurality of ports that communicatively couple the computer systems to the shared I/O subsystem where each of the ports includes at least one corresponding bit in an adjustable span port register. Data packets arriving on the plurality of ports may be selectively provided to a span port based on a current state of the adjustable span port register.

System and method for span port configuration

An integrated circuit has digital logic that supports two or more different processing speeds and two or more different data rates that are distinguished by each data rate having a data prefix at a different common-mode voltage. For normal processing, the integrated circuit has one or more comparators that compare the average signal voltage level with one or more reference voltages to determine the data rate. According to one embodiment of the invention, one or more muxes are configured between the comparators and the digital logic. These muxes can be controlled during testing to by-pass the operations of the comparators to pass specified digital codes to the digital logic to simulate the operations of the comparators. In this way, the different processing speeds of the digital logic can be tested without having to build special automatic test equipment to support all of the different possible voltage levels corresponding to the different supported data rates.

Speed-signaling testing for integrated circuits

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Lansdale, PA, United States of America

Joseph David Coyne