Xilinx, Inc.

Zycad Corporation

Actel Corporation, Inc.

Joseph D Linoff

Gary R Lawman

James L Burnham

Robert W Wells

Stephen L Wasson

Timothy Saxe

Richard D Freeman

A field programmable gate array (FPGA) is provided that can selectively accept or reject selected software (macros). Specifically, configuration data for the FPGA is passed through a configuration port to a decoder. The decoder processes the configuration data to detect locked macros. If a locked macro is detected, the decoder attempts to unlock the locked macro using one or more keys stored in a key table of the FGPA. If an appropriate key is in the key table, the decoder unlocks the locked macro to configure the FPGA. The keys can be pre-programmed into the FGPA by the macro vendor. If configuration data containing a locked macro is used with an FPGA without the appropriate key, configuration of the FPGA fails.

FPGA customizable to accept selected macros

A method is provided for configuring an FPGA to accept or reject selected software (macros). Specifically, if an end user desires to use a locked macro from a first macro vendor a locked macro from a second macro vendor in the same FPGA, a key manager prepares a keyed FPGA for the end user by pre-programming an FPGA with a first key, which is configured to unlock the first locked macro, and a second key, which is configured to unlock the second locked macro. The key manager obtains the first key from the first macro vendor and the second key from the second macro vendor. The keys are stored in a key table of the FPGA that is write-only from outside the FPGA. The end user pays a fee to the key manager for the keyed macro, but is not given access to the keys. The key manager apportions the fee from the end user and distributes appropriate licensing fees to the first macro vendor and the second macro vendor.

Methods to securely configure an FPGA to accept selected macros

A method of specifying design parameters is provided for configuring circuits for programmable ICs. A design database describing a circuit is displayed in table-based format on a computer screen display. The design database may include a memory map including data to be placed in bit-storage space in the target programmable IC. This design database requires no schematics or HDL description of the circuit, even for complicated application-specific circuits. The desired parameters are entered by the user, typically using toggle buttons, pull-down menus, or keyboard entry. The selected parameters are then entered into the design database, thereby configuring the design database in accordance with the selected parameters. Next, the design database is transmitted over a data communications link such as the internet to a second computer, on which the compilation software resides. The design is then compiled and the resulting netlist is transmitted back to the originating computer. In one embodiment, a schematic symbol or HDL instantiation is also generated by the second computer, and transmitted back to the originating computer.

Method for configuring circuits over a data communications link

A table-based computer user interface and a method of providing design parameters are provided for configuring circuits for programmable ICs. A design database describing a circuit is displayed in table-based format on a computer screen display. The design database may include a memory map including data to be placed in bit-storage space in the target programmable IC. This design database requires no schematics or HDL description of the circuit, even for application-specific circuits and other complicated circuits. The desired parameters are entered by the user, typically using toggle buttons, pull-down menus, or keyboard entry. The selected parameters and memory map data are then entered into the design database, thereby configuring the design database in accordance with the selected parameters. In one embodiment, the user interface can also be used to display read data from a previously programmed programmable IC.

Memory map computer control system for programmable ICS

A system and method for altering the effective operating frequency of an electronic system (e.g., an IC) in response to changes in temperature or current provides controlled and deliberate performance degradation. Reducing the effective operating frequency at high temperatures allows an IC to maintain a relatively stable power consumption. A first embodiment of the invention includes a temperature transducer, an Analog-to-Digital (A/D) converter, a select generator, and a clock frequency divider. The temperature transducer measures the temperature, which is converted by the A/D converter to a digital value. The digital temperature value drives the select generator, which generates one or more select signals. The select signals control the clock frequency divider to produce a clock signal with an effective clock frequency that depends on the measured temperature. According to a second embodiment of the invention, a current transducer is used instead of a temperature transducer.

System and method for controlled performance degradation in electronic

The present invention provides a novel clock frequency divider that accepts an input clock having an input clock frequency and provides an output clock with an effective clock frequency of one of 1/N, 2/N, . . . , (N-1)/N, N/N times the input clock frequency, where N is an integer. The clock frequency divider of the present invention divides the input clock frequency asymmetrically by filtering out one or more of each N pulses on the input clock, as dictated by select signals. For example, in a clock frequency divider having N=8, a first clock output signal filters out one of each eight pulses, retaining seven pulses. Therefore, the effective frequency of the output clock signal is (N-1)/N, or 7/8, times the frequency of input clock signal. Similarly, a second output clock signal retains six of every eight pulses, a third retains five, and so forth.

Circuit and method for generating clock signals with an incrementally

The present invention provides for an FPGA integrated circuit having an array of logic cells and interconnect lines interconnected by programmable switches, each formed from a nonvolatile memory cell. The logic cell is designed to provide logic or memory functions according to the setting of programmable switches within the cell. The logic cells in the array are interconnectable by a hierarchy of local, long and global wiring segments. The interconnections are made by the setting of programmable switches between the wiring segments.

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San Jose, CA, United States of America

Joseph D Linoff