Vtc Inc.

Joseph D Giacomini

A differential transimpedance amplifier with reduced input impedance and increased bandwidth having a pair of input contacts, a pair of summing transistors, a pair of feedback transistors, a pair of output resistors, a pair of feedback resistors, a first and a second node and a pair of output contacts. The input contacts each being connected to one or more sources of current that are to be summed and are connected to the pair of summing transistors. The pair of feedback transistors are connected to the pair of input contacts, the pair of feedback resistors and to the first node for differentially reducing the input impedance of the pair of summing transistors and to overcome voltage excursions at the pair of input contacts to increase the operational bandwidth of the transimpedance amplifier. The pair of output resistors are connected to the pair of summing transistors for converting the current sum for each input contact into a voltage level that is transmitted differentially by the pair of output contacts that are connected to the pair of summing transistors.

Differential transimpedance amplifier

A multiplying digital-to-analog converter produces first and second output currents that have a magnitude difference equal to a gain value multiplied by a magnitude difference between first and second input currents. The multiplying digital-to-analog converter has first and second input nodes for carrying the first and second input currents and first and second output nodes for carrying the first and second output currents. A first input transistor has a first terminal coupled to the first input node, a second terminal with voltage that increases with increases in the first input current, and a third terminal for carrying a first input bias current. A second input transistor has a first terminal coupled to the second input node, a second terminal with a voltage that increases with increases in the second input current, and a third terminal for carrying a second input bias current. A first output transistor has a first terminal coupled to the first output node, a second terminal coupled to a second terminal of the first input transistor, and a third terminal for carrying a first output bias current. A similar second output transistor has a third terminal for carrying a second output bias current. A first output bias circuit between a reference voltage and the third terminals of the first and second output transistors includes a gate transistor receiving a gate input signal, wherein the gate transistor is the only element in the first output bias circuit that is capable of receiving a signal other than the first and second output bias currents and the reference voltage.

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Eagan, MN, United States of America

Joseph D Giacomini