Cypress Semiconductor Corporation

Joseph D Caliston

Khushrav S Chhor

William R Orso

An apparatus, method and kit is provided for aligning small, closely spaced leads of an integrated circuit to small, closely spaced test conductors within a test apparatus. The leads can be arranged in various ways, and can extend from dissimilar types of integrated circuit packages. Likewise, the test conductors can be configured from a test socket possibly within a test head. The integrated circuit or DUT is forwarded toward the test conductors by a handler. The kit is used to secure the DUT and align the leads with the test conductors. Alignment can be achieved in either two or three dimensions. According to one embodiment, the kit includes a test socket unique to the DUT having at least one pin, and preferably two pins, extending from the test socket through an insert, also provided with the kit. T he insert retains the DUT and the opening within the insert extends over the pin to effectuate two-dimensional alignment. A spacer may also be provided with the kit as an alternative embodiment. The spacer can be affixed to the test socket outside the test conductors. The spacer operates similar to a shim and is designed to abut between the test socket and the insert. A change in the thickness of the spacer will modify the spacer thickness will provide alignment in a third dimension so that optimal electrical contact is achieved between leads and test conductors.

Growing community of inventors

Bacolod, Philippines

Joseph D Caliston