International Business Machines Corporation

Lenovo (singapore) Pte. Ltd.

International Business Corporation

Joseph Curtis Diepenbrock

Roland Frech

Bruce Roy Archambeault

Robert Joseph Evans

Kamran Amini

Bhyrav M Mutnury

Brian Samuel Beaman

Tin-Lup Wong

Richard Allen Kelley

Joseph Anthony Holung

Samuel R Connor

Daniel N De Araujo

Michael Leo Scollard

Robert J Christopher

Price Ward Oman

Hartmut Ulland

Leonard Douglas Hobgood

Frank J Pita

Phillip R Epley

Guenter Hahn

Marcel B Tran

Mike L Scollard

Donald J DaCosta

Klaus Muenzner

A method and associated system for evaluating a high-frequency signal (S) at a point of interest on a signal path. The high-frequency signal (S) at the point of interest on the signal path is calculated by applying an inverse transfer function (iG) for the signal path to an argument of a remote signal (S) measured at a remote pickup point on the signal path, wherein the point of interest and the remote pickup point are two distant points on the signal path, wherein the high-frequency signal (S) and the remote signal (S) are represented as a respective time domain variable, and wherein said calculating is performed by a time domain evaluation process that operates in test equipment for electrical devices. The calculated high-frequency signal (S) is transferred to an output device of the test equipment.

Evaluating high frequency time domain in embedded device probing

A system and associated method for evaluating a high-frequency signal at a point of interest on a signal path from a remote signal at a remote pickup point on the signal path. The point of interest is located on a device under test that is coupled to test equipment via the signal path. The high-frequency signal at the point of interest is calculated from the remote signal at the remote pickup point with an inverse transfer function that eliminates degradation effects on the high-frequency signal that is transferred through the signal path. The inverse transfer function may be calculated from measurements acquired in a test signal transfer through a reference path that simulates electrical properties of the signal path, or configured to a predetermined function if electrical properties of the signal path are known.

System and method for evaluating high frequency time domain in embedded device probing

A cable for high speed data communications and method of manufacturing the cable, the cable including a first inner conductor enclosed by a first dielectric layer and a second inner conductor enclosed by a second dielectric layer, the inner conductors and the dielectric layers twisted in a rotational direction at a periodic rate along and about a longitudinal axis and conductive shield material wrapped in the rotational direction at the periodic rate along and about the longitudinal axis around the inner conductors and the dielectric layers, including overlapped wraps at the periodic rate along and about the longitudinal axis. Transmitting signals on the cable including transmitting a balanced signal characterized by a frequency in the range of 7-9 gigahertz on the cable.

Cable for high speed data communications

A signal channel extends from motherboard to a daughter card across an edge connection. The daughter card includes a conductive plane that is held at a constant electrical potential. In order to compensate for a number of sources of inductance within the signal line at the edge connection, a circuit trace forming a portion of the signal channel includes an enlarged portion, spaced inward along the daughter card from the contact pads forming the edge connection, that adds capacitive coupling of the signal channel with the conductive plane.

Signal channel configuration providing increased capacitance at a card edge connection

A terminator assembly for a twinax wire. According to this embodiment, a PCB is provided which receives the twinax wire and provides a positive connection between a grounding bar of the PCB and the drain wide of the twinax pair. The drain wire is extended in an orthogonal direction to the twinax pair, and is engaged using an interference fit with the grounding bar. The grounding bar assembly also provides improved shielding for the twinax pair, where the integral shielding of the twinax wire has been removed to provide the connection. In an alternate embodiment, the terminating end of the twinax wire itself is encased in a termination clip. This clip provides shielding for the twinax pair, while electrically connecting with the twinax drain wire. The twinax wire, with the terminating clip, can then be easily attached to a connector PCB adapted to receive the terminator clip.

Enhanced wire termination for twinax wires

A computer processor socket has a base with grounding and signal holes. Each hole contains a pin for electrical interconnection with a circuit board. The socket also contains a grounding device around its perimeter. The grounding device has a continuous ring of wiping members on its upper end. When a processor is mounted to the top of the socket, the wiping members extend slightly above the processor. The heatsink mounted on top of the processor engages the wiping members which are spring-biased against its lower surface. Since the wiping members extend completely around the perimeter of the socket, a continuous electrical ground interface is formed between the heatsink and the socket. The lower ends of the grounding device are electrically interconnected with the socket grounding pins which are grounded to the board.

Electrical grounding schemes for socketed processor and heatsink assembly

A printed circuit board connector edge tab design has increased tab contact area with a large local capacitance at the connector interface. This serves to balance out the inductive effects of the connector and results in a lower overall channel impedance at the interface. The invention replaces the prior art plated pathway to the upper row of tabs with wider tabs on the lower row. The edges of the lower row tabs are spaced such that each of the connector pins destined for the upper row straddle two of the lower tabs as they travel upward. This design prevents the pins from contacting the fiberglass substrate of the board while it traverses the lower row of tabs. The absence of the prior art plated pathways allows each of the lower row tabs to be expanded into the space formerly occupied by the pathways. This design also allows the increased capacitive area of the edge tabs to be located in very close proximity to the connection area between the connector pins and the edge tabs.

Circuit board connector edge with straddle pattern tab design for impedance-controlled connections

The invention is related to hot plugging of an electrical circuit (1) into a separate non-quiesced signal net (6) in an active system (7), such as a digital or analog bus. The inventive solution proposes the addition of a preconditioning network (4) to precondition the electrical circuit (1) to be hot plugged by partially precharging the parasitic input capacitances (C.sub.c, C.sub.e, C.sub.m) of the electrical circuit (1) before hot plugging. The precharging of the parasitic input capacitances serves to minimize transient effects on the active system (7).

Precharge for non-disruptive bus live insertion

A high-speed data transport system for use in computers, switches, microprocessors or the like includes a low impedance differential bus and a plurality of transceivers connected to the bus. Each of the transceivers is provided with a driver circuit which places data onto the bus and a receiver for accepting data from the bus. The driver includes a pseudo-differential current driving circuit arrangement which sinks current from only one side of the bus while the other side of the differential bus is undisturbed. The receiver includes a differential comparator biased to a preferred output voltage level.

High speed bus transceiver with fault tolerant design for hot pluggable

Growing community of inventors

Raleigh, NC, United States of America

Joseph Curtis Diepenbrock