Lsi Logic Corporation

Csr Technology Inc.

Zoran Corporation

Teralogic, Inc.

Joseph Cesana

David R Auld

Aleksandr M Movshovich

Gerard K Yeh

Bruce Holmer

Peter Trajmar

Hsiang O-Yang

Zeljko Markovic

Jackson F Lee

Xianliang Zha

Monica Tang

Hank Guo

Edward Wang

Steve Chiou

Systems and methods of processing a video signal are provided. A potential block boundary can be detected between a first block and a second block of a frame of the video signal, wherein the frame, the first block, and the second block each include a plurality of pixels. An offset parameter can be determined for at least one pixel of at least one of the first block and the second block. Based on the offset parameter, a boundary verification value of at least one of the first block and the second block can also be determined. Based on the boundary verification value, it can further be determined if the potential block boundary includes a block boundary.

Method and apparatus for video signal processing

A method and an apparatus for an integrated high definition television controller are described. The integrated high definition digital television controller includes two or more the following functions in a single chip: MPEG2 Transport, Audio and Video Decoders, Video input capture and converter, flexible video scan rate converter, de-interlace processor, display controller and video D/A converters, graphics controller, a unified local bus, N-plane alpha blending, a warping engine, audio digital signal processor, disk drive interface, peripheral bus interfaces, such as PCI bus and local bus interfaces, various I/O peripherals, a bus bridge with a partitioned chip, and a CPU with caches. The integrated controller, in one embodiment, is designed to handle multiple television standards (for example ATSC, ARIB, DVB, AES, SMPTE, ITU) and designed to be deployed in various countries in the world.

Method and apparatus for an integrated high definition television controller

A method and apparatus for display of graphical data is described. The invention provides an architecture for graphics processing. The architecture includes pipelined processing and support for multi-regional graphics. In one embodiment, a graphics driver according to the invention can receive multiple independent streams of graphical data that can be in different graphical formats. The independent streams are synchronized and converted to a common format prior to being processed. In one embodiment, multi-regional graphics are supported with off-screen and on-screen memory regions for processing. The regions of the multi-regional graphic are rendered in an off-screen memory. The data in the off-screen memory are converted to a common format and copied to on-screen memory. The data in the on-screen memory is used to generate an output image. Alpha blending can also be programmed to provide multi-regional graphics or other graphical features. In one embodiment, graphics processing is programmable and can be paced using a set of registers.

Graphics engine architecture

An instruction swap is implemented in a dual pipelined microprocessor to make instruction flow smoother upon resource or structural conflicts in executing an instruction. Instructions are accessed in an even and odd pair with an even instruction proceeding an odd instruction. The accessed instructions are stored in Read/Decode registers for decoding and execution. The even and odd instructions are swapped in the registers and in execution when the preceding even instruction encounters an execution conflict or a branch.

Instruction swapping in dual pipeline microprocessor

Growing community of inventors

Palo Alto, CA, United States of America

Joseph Cesana