Motorola Corporation

Joseph Carbonaro

Jesse R Wilson

Richard B Reis

R A Garibay, Jr

A design for a structured scan path circuit incorporating domino logic circuitry is provided. The scan path circuit allows the rapid evaluation of a predetermined logic function, while allowing the use of automatic test pattern generation programs. Each function input signal has its own latch, the equivalent to the master latch in a standard scan flip-flop. The domino function output also has a latch, the equivalent of the slave latch in the scan flip-flop. The use of the input latches eliminates the need to insure the stability of the function input signals during the evaluation of the domino logic function. Thus, the input latches eliminate the potential 'hazard' problems which can occur due to the instability of the input signals during evaluation of the domino logic function. A scan enable signal selectively enables and disables the function evaluation by the domino logic circuitry. Thus, the function evaluation may be disabled for a 'capture' interval, to allow the scan circuit to scan in a scan data value, and scan out the same scan data value, via the slave on the function output. The scan circuit also incorporates decoder circuitry to further increase the speed at which the scan path circuit evaluates the logic function.

Structured scan path circuit for incorporating domino logic

A binary magnitude comparator having a plurality of rows and a plurality of columns, including a most significant column and a least significant column. The binary magnitude comparator is not clocked and performs a comparison asynchronously in a shorter period of time than a clocked binary magnitude comparator of corresponding bit size. The binary magnitude comparator comprises a plurality of comparator cells forming a plurality of rows and columns. Each row corresponds to a register, and each column a bit position in that register. A comparison is begun by selecting one or more registers with a plurality of select signals coupled to comparator cells in the most significant column, and proceeds from the most significant column, to successively next most significant columns, and terminates when the comparison in the least significant column is complete. The result of the binary magnitude comparison is a first output signal representing a binary value of a highest-valued register, and a second output signal, indicating which row or rows had the highest value. The binary magnitude comparator is designed to operate with an arbitrary number of rows and columns.

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Joseph Carbonaro