Teletype Corporation

At&t Teletype Corporation

Joseph C Zuercher

Raymond R Christian

Herbert A Waggener

Harry Sue

A nozzle structure in a crystallographically oriented, monocrystalline silicon includes a pyramidal opening anisotropically etched from the entrance side of the nozzle and truncated in a membrane having a smaller cross-section than the initial cross-section of the entrance opening. The membrane has extending therethrough a pyramidal opening etched anisotropically from the exit side. The vertical axes of both openings are substantially concentric.

Silicon nozzle structures and method of manufacture

An integrated circuit 14 having an active circuit 19 is formed on a circuit wafer 10. A moat 18 in the field oxide 20 surrounds the active circuit 19. Metallic conductor 30 passes from a location on the active circuit 19 over the moat 18 to a contact area 22. The wafer 10 is covered with a photoshaped silicon nitride layer 18, and a support wafer 40 is secured with adhesive 46 to the circuit side of the circuit wafer 10. The circuit wafer 10 is photoshaped to expose the metallic conductor 30 at the contact area 22, and the contact area 22 is prepared with multiple metal layers 62, 66, 70 for connection to external wiring.

Method for manufacturing an integrated circuit device

A method for manufacturing an integrated circuit thermal print head is illustrated including transistor 20 and a resistor doped region 22 formed on a first surface of a silicon circuit wafer 10. A contamination barrier in the form of a moat 26 filled with silicon nitride 30 is formed around the transistor 20. A support wafer 50 is secured to the first surface of the circuit wafer 10 by an adhesive layer 58. The circuit wafer 10 is thinned, and the exposed surface of the circuit wafer 10 is photoshaped to define wafer segments 68 positioned over the resistor doped region 22.

A method for manufacturing an integrated circuit device illustrates the preparation of the first surface of a circuit wafer including the placement of fine alignment indicia 34a outside the active chip area. A support wafer 50 is secured to the first surface of the circuit wafer 10 by an adhesive layer 58. The circuit wafer 10 is thinned. Openings 66 are photoshaped in the circuit wafer 10 using wafer flats 51 for alignment. The openings expose alignment indicia 34a which are relief images in the adhesive of the alignment pattern 34. The exposed surface of the circuit wafer 10 is photoshaped, using the indicia 34a for alignment, to define wafer segments 68 positioned over resistor doped regions 22.

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Wilmette, IL, United States of America

Joseph C Zuercher