Texas Instruments Corporation

Pdf Solutions, Incorporated

Joseph C Davis

Purnendu K Mozumder

Richard Gene Burch

Christopher Hess

Dennis Ciplickas

Larg H Weiland

Sharad Saxena

Karthik Vasanth

Sherry F Lee

John Kibarian

Kimon Michaels

Brian E Stine

David M Stashower

Suraj Rao

Chenjing L Fernando

Rakesh Vallishayee

Gabriel George Barna

E Ajith Amerasekera

Pushkar Prabhakar Apte

Christoph Dolainsky

Jonathan O Burrows

Howard Read

Shian-Wei Aur

A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process. These yield predictions are then used to determine which areas in the fabrication process require the most improvement.

System and method for product yield prediction

A hot spot is identified within a mask layout design. The hot spot represents a local region of the mask layout design having one or more feature geometries susceptible to producing one or more fabrication deficiencies. A test structure is generated for the identified hot spot. The test structure is defined to emulate the one or more feature geometries susceptible to producing the one or more fabrication deficiencies. The test structure is fabricated on a test wafer using specified fabrication processes. The as-fabricated test structure is examined to identify one or more adjustments to either the feature geometries of the hot spot of the mask layout design or the specified fabrication processes, wherein the identified adjustments are capable of reducing the fabrication deficiencies.

Method for improving mask layout and fabrication

A yield for an integrated circuit is predicted by processing a wafer to have a portion fabricated with at least one layout attribute of the integrated circuit. The portion of the wafer is analyzed to determine an actual yield associated with the at least one layout attribute. A systematic yield associated with the at least one layout attribute is determined based on the actual yield and a predicted yield associated with the at least one layout attribute. The predicted yield assumes that random defects are the only yield loss mechanism. A yield of an actual or proprosed product layout is predicted for the integrated circuit based on the systematic yield.

An operational lifetime, and also performance characteristics, can be accurately predicted for an experimental transistor design ( ) and a specified set of fabrication process conditions ( ), without actually fabricating and testing a physical transistor made according to the particular design data and process conditions. With respect to the prediction of an operational lifetime, the operational lifetime can be expressed as a function of the size of a gate overlap ( ) of the transistor, and this relationship is valid throughout a selected semiconductor technology for which the transistor is designed. The size of the gate overlap is determined by selecting a combinations of values for two process conditions.

Method and apparatus for predicting an operational lifetime of a transistor

A semiconductor processing tool evaluation and design method which replaces tool specifications with a requirements region plus associated evaluation functions for iterative feedback tool design.

Equipment evaluation and design

Integration of dual voltages on a single chip can be accomplished with a minimum of extra masks by optimizing only the MDD implant of the peripheral transistors, while other implants remain the same for both transistor types. This meets lifetime specifications without unnecessary expense.

Integrating dual supply voltages using a single extra mask level

A method and system for providing optimal tuning for complex simulators. The method and system include initially building at least one RSM model having input and output terminals. Then there is provided a simulation-free optimization function by constructing an objective function from the outputs at the output terminals of the at least one RSM model and experimental data. The objective function is optimized in an optimizer and the optimized objective function is fed to the input terminal of the RSM. Building of at least one RSM model includes establishing a range for the simulation, running a simulation experiment for the designed experiment, extracting relevant data from said experiment and building the RSM model from the extracted relevant data. The step of running a simulation experiment comprises the step of running a DOE/Opt operation. The objective function is, for example, the square root of the sum of the squares at all of the differences between the target values and the observed values at all points being investigated. The optimizing in the optimizer is preferably a gain function which adjusts the parameters to the input based upon the error signal to minimize the error signal.

Method and system for using response-surface methodologies to determine optimal tuning parameters for complex simulators

Method for adequately modeling process induced variabilities is disclosed that comprises the steps of acquiring experimental data and defining a particular design space. Values for the mean and standard deviation of the experimental data at each of the points defining the design space are calculated. The experimental values of the output parameters at each of the design points is normalized to extract the shape of the distribution of each of the design points. The normalized values are then merged to form a cumulative distribution function associated with the data. The cumulative distribution function is applied to a new design point in a predicted fashion by first calculating a mean and standard deviation value for the new point by interpolating from the mean and standard deviation values from the experimental data. The cumulative distribution function is then scaled and centered using the interpolated mean and standard deviation values to provide a predicted data distribution for the new design point.

System and method for non-parametric modeling of processed induced variability

A statistical design method is provided for minimizing the impact of manufacturing variations on semiconductor manufacturing by statistical design which seeks to reduce the impact of variability on device behavior. The method is based upon a Markov representation of a process flow which captures the sequential and stochastic nature of semiconductor manufacturing and enables the separation of device and process models, statistical modeling of process modules from observable wafer states and approximations for statistical optimization over large design spaces. The statistical estimation component of this method results in extremely accurate predictions of the variability of transistor performance for all of the fabricated flows. Statistical optimization results in devices that achieve all transistor performance and reliability goals and reduces the variability of key transistor performances.

Design of microelectronic process flows for manufacturability and performance

A dual voltage chip is fabricated with no intermediate-doped (LDD or MDD) area in the high-voltage transistors by adjusting the gate sidewall spacer thickness and the source/drain implant.

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Allen, TX, United States of America

Joseph C Davis