Intersil Americas Inc.

University of Central Florida Research Foundation Inc

Other

Intersil Corporation

Joseph C Bernier

Donald K Whitney, Jr

Juin Jei Liou

Javier A Salcedo

Rex Everett Lowther

Gregg D Croft

Symmetrical/asymmetrical bidirectional S-shaped I-V characteristics with trigger voltages ranging from 10 V to over 40 V and relatively high holding current are obtained for advanced sub-micron silicided CMOS (Complementary Metal Oxide Semiconductor)/BiCMOS (Bipolar CMOS) technologies by custom implementation of P-N-P-N//N-P-N-Plateral structures with embedded ballast resistanceA,A and periphery guard-ring isolation-. The bidirectional protection devices render a high level of electrostatic discharge (ESD) immunity for advanced CMOS/BiCMOS processes with no latchup problems. Novel design-adapted multifinger/interdigitatedlayout schemes of the ESD protection cells allow for scaling-up the ESD performance of the protection structure and custom integration, while the I-V characteristicsare adjustable to the operating conditions of the integrated circuit (IC). The ESD protection cells are tested using the TLP (Transmission Line Pulse) technique, and ESD standards including HBM (Human Body Model), MM (Machine Model), and IEC (International Electrotechnical Commission) IEC 1000-4-2 standard for ESD immunity. ESD protection performance is demonstrated also at high temperature (140&#xb0; C.). The unique high ratio of dual-polarity ESD protection level per unit area, allows for integration of fast-response and compact protection cells optimized for the current tendency of the semiconductor industry toward low cost and high density-oriented IC design. Symmetric/asymmetric dual polarity ESD protection performance is demonstrated for over 15 kV HBM, 2 kV MM, and 16.5 kV IEC for sub-micron technology.

Devices with adjustable dual-polarity trigger- and holding-votage/current for high level of electrostatic discharge protection in sub-micron mixed signal CMOS/BiCMOS integrated

Symmetrical/asymmetrical bidirectional S-shaped I-V characteristics with trigger voltages ranging from 10 V to over 40 V and relatively high holding current are obtained for advanced sub-micron silicided CMOS (Complementary Metal Oxide Semiconductor)/BiCMOS (Bipolar CMOS) technologies by custom implementation of P-N-P-N//N-P-N-Plateral structures with embedded ballast resistanceA,A and periphery guard-ring isolation-. The bidirectional protection devices render a high level of electrostatic discharge (ESD) immunity for advanced CMOS/BiCMOS processes with no latchup problems. Novel design-adapted multifinger/interdigitatedlayout schemes of the ESD protection cells allow for scaling-up the ESD performance of the protection structure and custom integration, while the I-V characteristicsare adjustable to the operating conditions of the integrated circuit (IC). The ESD protection cells are tested using the TLP (Transmission Line Pulse) technique, and ESD standards including HBM (Human Body Model), MM (Machine Model), and IEC (International Electrotechnical Commission) IEC 1000-4-2_standard for ESD immunity. ESD protection performance is demonstrated also at high temperature (140&#xb0; C.). The unique high ratio of dual-polarity ESD protection level per unit area, allows for integration of fast-response and compact protection cells optimized for the current tendency of the semiconductor industry toward low cost and high density-oriented IC design. Symmetric/asymmetric dual polarity ESD protection performance is demonstrated for over 15 kV HBM, 2 kV MM, and 16.5 kV IEC for sub-micron technology.

Devices with adjustable dual-polarity trigger-and holding-voltage/current for high level of electrostatic discharge protection in sub-micron mixed signal CMOS/BiCMOS integrated

A complementary SCR-based structure enables a tunable holding voltage for robust and versatile ESD protection. The structureare n-channel high-holding-voltage low-voltage -trigger silicon controller rectifier (N-HHLVTSCR) device and p-channel high-holding-voltage low-voltage -trigger silicon controller rectifier (P-HHLVTSCR) device. The regions of the N-HHLVTSCR and P-HHLVTSCR devices are formed during normal processing steps in a CMOS or BICMOS process. The spacing and dimensions of the doped regions of N-HHLVTSCR and P-HHLVTSCR devices are used to produce the desired characteristics. The tunable HHLVTSCRs makes possible the use of this protection circuit in a broad range of ESD applications including protecting integrated circuits where the I/O signal swing can be either within the range of the bias of the internal circuit or below/above the range of the bias of the internal circuit.

On-chip structure for electrostatic discharge (ESD) protection

Devices with adjustable dual-polarity trigger- and holding-voltage/current for high level of electrostatic discharge protection in sub-micron mixed signal CMOS/BiCMOS integrated circuits

An electrostatic discharge (ESD) device and method is provided. The ESD device can comprise a substrate doped to a first conductivity type, an epitaxial region doped to the second conductivity type, and a first well doped to the first conductivity type disposed in the substrate. The first well can comprise a first region doped to the first conductivity type, a second region doped to a second conductivity type, and a first isolation region disposed between the first region and the second region. The ESD device can also comprise a second well doped to a second conductivity type disposed in the substrate adjacent to the first well, where the second well can comprise a third region doped to the first conductivity type, a fourth region doped to the second conductivity type, and a second isolation region disposed between the third region and the fourth region. Still further, the ESD device can include a first trigger contact and second trigger contact comprising highly doped regions of either conductivity type, the first trigger contact disposed at a junction between the first well and the second well, and the second trigger contact disposed at either well.

Electrostatic discharge protection device for digital circuits and for applications with input/output bipolar voltage much higher than the core circuit power supply

A complementary SCR-based structure enables a tunable holding voltage for robust and versatile ESD protection. The structure are n-channel high-holding-voltage low-voltage-trigger silicon controller rectifier (N-HHLVTSCR) device and p-channel high-holding-voltage low-voltage-trigger silicon controller rectifier (P-HHLVTSCR) device. The regions of the N-HHLVTSCR and P-HHLVTSCR devices are formed during normal processing steps in a CMOS or BICMOS process. The spacing and dimensions of the doped regions of N-HHLVTSCR and P-HHLVTSCR devices are used to produce the desired characteristics. The tunable HHLVTSCRs makes possible the use of this protection circuit in a broad range of ESD applications including protecting integrated circuits where the I/O signal swing can be either within the range of the bias of the internal circuit or below/above the range of the bias of the internal circuit.

A clipping apparatus for preventing tripping hazards caused by cords and simplifying installation of decorative lights having a tension clip. The tension clip is substantially U-shaped having an elongated member having two downwardly extending arms, each arm having a base. Each base has a small, V-shaped recessed channel through which a cord or strand of lights extends. A fully adjustable slide and click mechanism lengthens or shortens the elongated member of the tension clip. A pair of outwardly angled and extending fasteners define a simple clip mechanism attached to the elongated member and or one or both of the two arms for use in suspending the cord from tension clips installed upside down.

Clipping apparatus for attaching cords to walls

An electrostatic discharge locating system may include a plurality of receivers and a central unit. Each receiver may include an antenna. The receivers may receive radio wave signals emanating from an electrostatic discharge event and transmit the signals to the central unit for processing. The central unit may determine the location of an electrostatic discharge event from the relative time of signal reception or the signal amplitudes along with predetermined locations of the receivers.

Growing community of inventors

Palm Bay, FL, United States of America

Joseph C Bernier