Micron Technology Incorporated

Opcon Incorporated

Joseph B Wicklund

Ward D Parkinson

Geary L Leger

Karl H Mauritz

Steven H Laney

James E Herrud

A memory testing assembly (50) for testing a memory device under test ('DUT') includes a row address converter (58) and a column address converter (62). The row and column address converters translate generic row and column count signals into correct row and column address signals that address desired memory cells in a particular DUT. The row and column address converters comprise separate memory arrays, which allow them to employ a relatively small amount of memory bits. The row and column address converters are, however, cross-coupled to provide row and column information signals that are fed back to inputs of the respective column and row address converters. Such feedback allows the memory tester to be able to test DUTs for which some of the row addresses must be known to translate the column addresses and/or some of the column addresses be known to translate the row address. The memory tester writes data into the cells of the DUT and reads and compares the read data with the previously written data. The memory tester includes a data pattern generator (74) that controls the data topology of the data written into cells of the DUT.

Memory efficient topological converter assembly

A DRAM controller uses logic to selectively enable or disable a page mode of operation as a result of specific instructions from executing software, or upon some prediction of page mode efficiency based on past performance. An address multiplexer generates separate row and column addresses from the CPU address control lines, and to generate the necessary signals to control the timing of the RAS and CAS control signals that operate the DRAM. Page mode is automatically turned on or off based on a prediction of whether or not the next access will be at the same DRAM row address as the last one.

Semi-smart DRAM controller IC to provide a pseudo-cache mode of

A printed circuit board is designed to conform to a single in-line memory module (SIMM) configuration, but includes multiple rows of the memory devices. By controlling a sequence of enable signals, selection of a single row from the multiple row of memory devices can be accomplished. The ability to address the different rows multiplies the memory capacity of the board by the number of rows of memory devices.

Switched memory module

A balanced low impedance differential input line preamplifier comprising a differential amplifier and a pair of high gain common base input stages. The input signal is directly applied to the emitters of the common base input stages and the collectors of the common base input stages are each connected to one input of the differential amplifier. Capacitors are used to DC decouple the common base input stages to the differential amplifier.

Balanced low impedance differential input line preamplifier

The outputs of one or more interconnected, unbiased photovoltaic devices mounted to receive light generated by one or more modulated light sources are connected via a long cable to the input of a balanced low impedance differential input line preamplifier. When multiple photovoltaic devices are included, their outputs can be directly interconnected and the thusly combined output will provide information about the intensity of light impinging on their photo conductive surfaces. The balanced low impedance differential input line preamplifier comprises a differential amplifier and a pair of common base input stages, one connected to each input of the differential amplifier. In a DC decoupling embodiment, capacitors are used to couple the common base input stages to the differential amplifier. The output of the balanced low impedance differential input line preamplifier is connected to a detector that provides an output indicative of the state of the output of the photovoltaic devices.

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Bothell, WA, United States of America

Joseph B Wicklund