Mindspeed Technologies, Inc.

Cavium, Inc.

Conexant Systems, Inc.

Joseph B Tompkins

Wilson Parkhurst Snyder, Ii

Daniel J Lussier

Richard Eugene Kessler

Brian Folsom

Ethan Frederick Robbins

Andrew J Jones

Edwin Langevin

Bruce Burns

Wilson P Snyder Ii

Duane E Galbi

Duncan M Fisher

Michael A Tsukernik

Wilson P Snyder, Ii

Nagaraj G Shirali

Ranjith Kumar V Hallur

Jamie Mulderig

Krupa Sagar O S Mylavarapu

Mahesh Dorai

A circuit operates to manage transmittal of packets in a network packet processor. The circuit includes a packet descriptor manager (PDM), a packet scheduling engine (PSE), and a packet engines and buffering module (PEB). The PDM generates a metapacket and a descriptor from a command signal, where the command signal identifies a packet to be transmitted by the circuit. The PSE determines an order in which to transmit the packet among a number of packets, where the PSE determines the order based on information indicated in the metapacket. Once the packet is scheduled for transmission, the PEB performs processing operations on the packet to produce a processed packet based on instructions indicated in the descriptor. The PEB then causes the processed packet to be transmitted toward the destination.

Packet output processing

A circuit operates to manage transmittal of packets in a network packet processor. The circuit includes a packet descriptor manager (PDM), a packet scheduling engine (PSE), and a packet engines and buffering module (PEB). The PDM generates a metapacket and a descriptor from a command signal, where the command signal identifies a packet to be transmitted by the circuit. The PSE compares a packet transmission rate associated with the packet against at least one of a peak rate and a committed rate associated with the packet, and determines an order in which to transmit the packet among a number of packets based on the comparison. Once the packet is scheduled for transmission, the PEB performs processing operations on the packet to produce a processed packet based on instructions indicated in the descriptor. The PEB then causes the processed packet to be transmitted toward the destination.

Packet shaping in a network processor

A circuit operates to manage transmittal of packets in a network packet processor. The circuit includes a packet descriptor manager (PDM), a packet scheduling engine (PSE), and a packet engines and buffering module (PEB). The PDM generates a metapacket and a descriptor from a command signal, where the command signal identifies a packet to be transmitted by the circuit. The PSE models the packet through a model of the network topology, determining an order in which to transmit the packet among a number of packets based on the modeling. Once the packet is scheduled for transmission, the PEB performs processing operations on the packet to produce a processed packet based on instructions indicated in the descriptor. The PEB then causes the processed packet to be transmitted toward the destination.

Packet scheduling in a network processor

An integrated circuit processes communication packets and comprises a pointer cache and control logic. The pointer cache store pointers that correspond to external buffers that are external to the integrated circuit and configured to store the communication packets. The control logic allocates the external buffers as the corresponding pointers are read from the pointer cache and de-allocates the external buffers as the corresponding pointers are written back to the pointer cache.

Integrated circuit that processes communication packets with a buffer management engine having a pointer cache

Various systems and methods for buffer memory management are disclosed. In one embodiment a buffer memory includes at least one queue configured to store a number of buffer access tasks. Buffer reclamation logic is executed to free at least one segment of the buffer memory holding an amount of stale data. Buffer reclamation logic is also included that enables the buffer reclamation logic to submit a buffer access task to the buffer memory based upon a total number of the buffer access tasks stored in the at least one queue.

Buffer memory management

Various systems and methods for error correction of instructions in an instruction cache coupled to a processor are provided. In one embodiment, a plurality of instructions stored in the instruction cache are fetched for execution by the processor, each of the instructions being fetched during a respective one of a plurality of instruction cycles of the processor. Error detection is performed for each of the instructions concurrently with the fetching of a respective one of the instructions.

Error correction in a cache memory

An integrated circuit for processing communication packets having separate data buffers and separate state information buffers. Each data buffer and each state information buffer (hereinafter termed resources) has an associated in-use counter. Multiple events can share the same resource. The counter associated with a resource is incremented when a resource becomes associated with a particular event. The counter associated with a resource is decremented when an event completes the use of that particular resource. When the in-use counter for a resource becomes zero, the in-use counter indicates that the resource is unassigned and that the resource can be assigned to a new event.

Method for automatic resource reservation and communication that facilitates using multiple processing events for a single processing task

An integrated circuit processes a communication packet and comprises a core processor and scheduling circuitry. The core processor executes a software application that directs the core processor to process the communication packet. The scheduling circuitry retrieves first scheduling parameters cached in a context buffer for the packet and executes a first algorithm based on the first scheduling parameters to schedule subsequent transmission of the communication packet.

Integrated circuit that processes communication packets with scheduler circuitry that executes scheduling algorithms based on cached scheduling parameters

An integrated circuit comprises co-processor circuitry and a core processor. The co-processor circuitry comprises context buffers and data buffers. The co-processor circuitry receives and stores one of the communication packets in one of the data buffers. The co-processor circuitry correlates the one communication packet with one of a plurality of channel descriptors. The co-processor circuitry associates the one data buffer with one of the context buffers holding the one channel descriptor to maintain the correlation between the one communication packet and the one channel descriptor. The co-processor circuitry prevents multiple valid copies of the one channel descriptor from existing in the context buffers. In some examples of the invention, this is accomplished by tracking a number of the data buffers associated with the one context buffer. The core processor executes a packet processing software application that directs the processor to process the one communication packet in the one data buffer based on the one channel descriptor in the one context buffer.

Integrated circuit that processes communication packets with co-processor circuitry to correlate a packet stream with context information

An integrated circuit processes communication packets and comprises a core processor and scheduling circuitry. The core processor executes a software application that directs the core processor to process the communication packets. The scheduling circuitry comprises multiple scheduling boards where at least some of the scheduling boards have multiple priority levels. The scheduling circuitry processes the scheduling boards to schedule and subsequently initiate transmission of the communication packets.

Integrated circuit that processes communication packets with scheduler circuitry having multiple priority levels

An integrated circuit processes communication packets and comprises co-processor circuitry and a core processor. The co-processor circuitry is configured to operate in parallel with the core processor. The co-processor circuitry receives and stores the communication packets in data buffers. The co-processor circuitry also determines a prioritized processing order. The core processor executes a packet processing software application that directs the processor to process the communication packets in the data buffers based on the prioritized processing order.

Growing community of inventors

Westborough, MA, United States of America

Joseph B Tompkins