Apple Inc.

Sun Microsystems, Inc.

Joseph Anthony Petolino, Jr

Guy Cote

Joseph P Bratt

Simon Wolfenden Butler

Suk Hwan Lim

D Amnon Silverstein

Gary R Lauterbach

William L Lynch

Sheng Lin

David Hayward

Chitresh Chandra Narasimhaiah

Kalon S Holdbrook

Systems and methods for down-scaling are provided. In one example, a method for processing image data includes determining a plurality of output pixel locations using a position value stored by a position register, using the current position value to select a center input pixel from the image data and selecting an index value, selecting a set of input pixels adjacent to the center input pixel, selecting a set of filtering coefficients from a filter coefficient lookup table using the index value, filtering the set of source input pixels to apply a respective one of the set of filtering coefficients to each of the set of source input pixels to determine an output value for the current output pixel at the current position value, and correcting chromatic aberrations in the set of source input pixels.

Raw scaler with chromatic aberration correction

Systems and methods for correcting intensity drop-offs due to geometric properties of lenses are provided. In one example, a method includes receiving an input pixel of the image data, the image data acquired using an image sensor. A color component of the input pixel is determined. A gain grid is determined by pointing to the gain grid in external memory. Each of the plurality of grid points is associated with a lens shading gain selected based upon the color of the input pixel. A nearest set of grid points that enclose the input pixel is identified. Further, a lens shading gain is determined by interpolating the lens shading gains associated with each of the set of grid points and is applied to the input pixel.

Systems and methods for lens shading correction

Systems and methods for processing raw image data are provided. One example of such a system may include memory to store image data in raw format from a digital imaging device and an image signal processor to process the image data. The image signal processor may include data conversion logic and a raw image processing pipeline. The data conversion logic may convert the image data into a signed format to preserve negative noise from the digital imaging device. The raw image processing pipeline may at least partly process the image data in the signed format. The raw image processing pipeline may also include, among other things, black level compensation logic, fixed pattern noise reduction logic, temporal filtering logic, defective pixel correction logic, spatial noise filtering logic, lens shading correction logic, and highlight recovery logic.

Systems and methods for raw image processing

An address translation unit includes a translation lookaside buffer (TLB), a miss queue, and a control unit. The TLB may store a plurality of address translations. The miss queue may store received address translation requests that missed in the TLB. The miss queue includes a plurality of entries. At least some entries may each store a respective address translation request and a corresponding identifier. The corresponding identifier of a given entry identifies another entry in the miss queue that stores another respective address translation request having a process ordering constraint that is the same as a process ordering constraint of the respective address translation request in the given entry. Address translations having a same ordering constraint that are linked together via the identifier belong to the same virtual miss queue. The control unit may process the received address translation requests in an order dependent upon the identifier.

Address translation unit with multiple virtual queues

In an embodiment, a TLB is partitioned into regions. The TLB may be set associative, and each section may include a portion of the locations in each way of the set associative memory. The TLB may reserve at least one of the sections for access by a subset of the request sources that use the TLB. For requests from the subset, the reserved section may be used and a location in the reserved section may be allocated to store a translation for a request from the subset that misses in the TLB. For requests for other request sources, the non-reserved section or sections may be used. In one embodiment, each way of the reserved section may be assigned to a different one of the request sources in the subset.

Translation lookaside buffer (TLB) with reserved areas for specific sources

The present invention solves the problems associated with the prior art by providing a latency prediction bit (LPB) to indicate the latency with which an instruction should be executed, implicitly indicating whether a data dependency is likely to exist and the likelihood of that dependency causing a hazard. In a processor according to the present invention, an instruction dependent upon a given LDI instruction is issued a given number of machine cycles after that LDI instruction, the number of machine cycles being based on the value of the LPB associated with that LDI instruction. The LPB's value, in turn, depends on whether data will need to be forwarded to the functional unit involved during the execution of LDI instruction. The ability to predict such hazards is important in maintaining a pipeline's throughput and avoiding unnecessary recirculations.

Latency prediction in a pipelined microarchitecture

The present invention solves the problems associated with the prior art by decoupling the issuing of instructions from their dispatch into their respective pipeline. This permits the determination of whether a particular instruction can safely be issued from an instruction queue to the next stage of the pipeline by providing such information at a point early in the machine cycle.

Apparatus for reducing instruction issue stage stalls through use of a

The present invention solves the problems associated with the prior art by decoupling the issuing of instructions from their dispatch into their respective pipeline. This permits the determination of whether a particular instruction can safely be issued from an instruction queue to the next stage of the pipeline by providing such information at a point early in the machine cycle. In a multistage pipeline, a first stage is bypassed to provide instructions to a second stage regardless of the ability of the first stage to store the instruction from the instruction issuing unit.

Method for decoupling pipeline stages

An apparatus for executing an instruction is provided. The instruction loads data into one of a plurality of registers in a register file and is in a first group of instructions. A second group of instructions is executed sequentially after the first group of instructions. The first and second groups of instructions should each include at least one instruction. The apparatus includes a first memory, a second memory, a first functional unit coupled to the first memory, and a second functional unit coupled to the first memory and to the second memory. The first and second functional units are both capable of executing the instruction. Also included is an instruction issue unit coupled to the first and the second functional units. The instruction issue unit issues the instruction to a selected functional unit selected from one of the first and the second functional units. This selection is based on a load prediction bit associated with the instruction.

Load instruction steering in a dual data cache microarchitecture

The present invention provides for a method and apparatus for reading non-cachable information in a cache memory system. The cache memory system includes a processor, a buffer, a multiplexor, main memory, an input/output unit, a cache controller, a memory management unit, and cache memory. In a read operation, the processor directs a read operation specifying a first address to the cache memory. The cache controller initially determines whether the information desired is cachable or non-cachable. If the information desired is determined to be non-cachable, the cache controller causes any information presently contained in a first location in the cache memory to be stored in the buffer. In the interim, the cache controller causes the memory management unit to initiate an access of the information desired from the first address. Once accessed, this information is temporarily written into the first location within the cache memory. From this first location within the cache memory, the information is coupled, as desired, to the processor. The cache controller then restores the information formerly in the first location, by coupling the contents of the buffer back into the first location within the cache memory.

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Palo Alto, CA, United States of America

Joseph Anthony Petolino, Jr