International Business Machines Corporation

Joseph Andrew Iadanza

Sebastian Theodore Ventrone

Anthony Richard Bonaccio

Hayden C Cranford, Jr

Igor Arsovski

Frank Ray Keyser, Iii

Scott Whitney Gould

Pradeep Thiagarajan

Terrance John Zittritsch

Kim P Clinton

Douglas Willard Stout

Serafino Bueti

Wagdi William Abadeer

Stephen Dale Wyatt

Hemen R Shah

Victor Paul Seidel

Ralph David Kilmoyer

Edward J Nowak

Todd Edwin Leonard

Ivan L Wemple

Jason Michael Norman

Steven Paul Hartman

Robert Glen Gerowitz

Makoto Ueda

Eric Ernest Millham

Michael Joseph Laramie

Sarah B Higgins

Benjamin T Voegeli

Brian A Worth

Allan Robert Bertolet

Timothy Shawn Reny

Christine Marie Fuller

Gulson Yasar

Kenneth Joseph Goodnow

George Maria Braceras

Alvar Antonio Dean

Mark Steven Styduhar

Raminderpal Singh

Corey Kenneth Barrows

Allen Prescott Haar

Wilfried E A Haensch

Rohit Pradeep Shetty

Daniel Joseph Friedman

Albert Manhee Chu

John Francis Bulzacchelli

James Stuart Dunn

Richard Stephen Graf

Mujahid Muhammad

David E Lackey

Todd Morgan Rasmus

Ram Kelkar

Josef S Watts

Jerry D Hayes

Bradford Lawrence Hunter

Jack Robert Smith

Carrie Ellen Cox

Eric Adler

Daryl Michael Seitzer

Bret Roberts Dale

Alfred Degbotse

Emory D Keller

Faraydon Pakbaz

Jonathan H Raymond

Jenifer E Lary

Zeynep Toprak-Deniz

Kent E Morrett

Hongfei Wu

Paul Alan Owczarski

Arnold E Baizley

Jane S Tu

Hayden (Clay) Cranford, Jr

Eirik Gude

Approaches for testing phase rotators are provided. A circuit for testing phase rotators includes a compare element including a first input and a second input, wherein the compare element is configured to compare a first phase of a first signal provided at the first input to a second phase of a second signal provided at the second input. The circuit also includes a first test bus connected to the first input and a second test bus connected to the second input.

Testing integrated circuit designs containing multiple phase rotators

Disclosed are embodiments of a design structure transistor that operates as a capacitor and an associated method of tuning capacitance within such a capacitor. The embodiments of the capacitor comprise a field effect transistor with front and back gates above and below a semiconductor layer, respectively. The capacitance value exhibited by the capacitor can be selectively varied between two different values by changing the voltage condition in a source/drain region of the transistor, e.g., using a switch or resistor between the source/drain region and a voltage supply. Alternatively, the capacitance value exhibited by the capacitor can be selectively varied between multiple different values by changing voltage conditions in one or more of multiple channel regions that are flanked by multiple source/drain regions within the transistor. The capacitor will exhibit different capacitance values depending upon the conductivity in each of the channel regions.

Tunable capacitor

An integrated circuit includes logic regions and dynamically adjustable voltage controllers. A voltage controller connected to each logic region enables voltage adjustment while the chip is operating. Each voltage controller has a selector device connected to voltage input lines providing different voltages. A voltage sensor connected to the output of the selector device provides a supply voltage to one of the logic regions. A control circuit dynamically monitors the supply voltage, captures and stores a digital representation of the supply voltage during each cycle of a clock, and tracks variations over time, based on operation of the logic regions. When variations in the supply voltage exceed an operational threshold of one of the logic regions, the control circuit submits a request to a central controller. When the central controller grants permission, the control circuit dynamically adjusts the voltage by enabling the selector device to choose a different voltage input line.

Real-time adaptive voltage control of logic blocks

A process of optimizing a resistor-2 resistor (R-2R) digital-to-analog converter (DAC) by partial resistor network reconfiguration is disclosed. The method includes analyzing a circuit to determine whether any specifications are outside predetermined limits. The method further includes determining one or more addresses that cause the circuit to be outside of the predetermined limits. The method further includes defining logic to detect address information and control function to alter the circuit to improve the specifications. The method further includes installing the control function into the circuit to improve the specifications.

Network reconfiguration in a data converter for improved electrical characteristics

Dual-loop voltage regulator circuits and methods in which a dual-loop voltage regulation framework is implemented with a first inner loop having a bang-bang voltage regulator to achieve nearly instantaneous response time, and a second outer loop, which is slower in operating speed than the first inner loop, to controllably adjust a trip point of the bang-bang voltage regulator to achieve high DC accuracy.

Dual-loop voltage regulator architecture with high DC accuracy and fast response time

A resistor-2 resistor (R-2R) digital-to-analog converter with partial resistor network reconfiguration. A circuit includes a plurality of resistor stacks. The circuit also includes a plurality of separation resistors which separate each of the plurality of resistor stacks. The circuit further includes a first selection circuit connected to a first resistor stack of the plurality of resistor stacks and a plurality of selection circuits connected between the plurality of separation resistors. The circuit also includes a termination resistor stack connected to a drain of the first resistor stack.

Resistor-2 resistor (R-2R) digital-to-analog converter with partial resistor network reconfiguration

A system and method of allocating a job submission for a computational task to a set of distributed server farms each having at least one processing entity comprising; receiving a workload request from at least one processing entity for submission to at least one of the set of distributed server farms; using at least one or more conditions associated with the computational task for accepting or rejecting at least one of the server farms to which the job submission is to be allocated; determining a server farm that can optimize the one or more conditions; and dispatching the job submission to the server farm which optimizes the at least one of the one or more conditions associated with the computational task and used for selecting the at least one of the server farms.

Environmental and computing cost reduction with improved reliability in workload assignment to distributed computing nodes

A resistor-2 resistor (R-2R) digital-to-analog converter with resistor network reversal and methods of use are disclosed. A circuit includes a plurality of resistor stacks and a plurality of separation resistors which separate the resistor stacks. The circuit further includes a plurality of selection devices connected to a respective one of the plurality of resistor stacks. The circuit also includes a first termination resistor stack connected to a drain of a first resistor stack of the plurality of resistor stacks and a second termination resistor stack connected to a drain of a last resistor stack of the plurality of resistor stacks. The circuit further includes a first switch connected to the drain of the first resistor stack of the plurality of resistor stacks and an output. The circuit also includes a second switch connected to the drain of the last resistor stack of the plurality of resistor stacks and the output.

Resistor-2 resistor (R-2R) digital-to-analog converter with resistor network reversal

Aspects of the invention provide an electrostatic discharge (ESD) protection device for eliminating current leakage, and a related method. In one embodiment, an ESD protection device includes: a resistor-capacitor (RC) circuit for receiving a power supply voltage; an ESD clamp including a plurality of n-type field-effect transistors (nFETs) for protecting the IC during an ESD event; a trigger circuit for receiving an output of the RC circuit and generating a trigger pulse to turn on the ESD clamp during the ESD event; and an nFET bias selection circuit connected to the trigger circuit, the nFET bias selection circuit for selecting one of: a low voltage supply or a negative bias voltage supply for the trigger circuit, such that the trigger circuit generates a trigger pulse, in response to selecting the negative bias voltage supply, to turn off the ESD clamp during normal operation.

Current leakage in RC ESD clamps

A differential system producing differential signals with offset cancellation utilizing a double differential input pair system is disclosed. It uses two parallel differential transistor pairs which are intentionally skewed. Nominally, the differential pairs are skewed in opposite direction from each, but with equal magnitude, so that the combination of the two differential pairs is nominally balanced. The current through each differential pair is then increased or decreased until any offset is sufficiently cancelled, using a selection means for providing an equi-potential value to first and second differential inputs in a calibration mode of the system and a comparison means for comparing first and second differential outputs in a calibration mode to determine the offset of the system.

Skewed double differential pair circuit for offset cancellation

A method and structure for preventing operation of a circuit in a high current operating region by disabling a start-up circuit until a power supply headroom is detected at a predetermined voltage level.

Low voltage head room detection for reliable start-up of self-biased analog circuits

Disclosed are embodiments of a variable-delay field effect transistor (FET) having multiple source regions that can be individually and selectively biased to provide an electrical connection to a single drain region. Delay is a function of which of the multiple source regions is/are selectively biased as well as a function of gate resistance and capacitance. Such a variable-delay FET can be incorporated into a phase adjusting circuit, which uses gate propagation delays to selectively phase adjust an input signal. The phase adjusting circuit can be tuned by incorporating non-salicided resistances and additional capacitance at various positions on the gate structure. The phase adjusting circuit can further be modified into a phase adjusting mixer circuit that enables a phase adjusted signal to be combined with an additional signal.

Multiple source-single drain field effect semiconductor device and circuit

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Hinesburg, VT, United States of America

Joseph Andrew Iadanza