Dell USA L P

Joseph A Vivio

Joshua Titus

Alan E Brown

Daniel L Bouvier

James S Bell

Victor K Pecone

Joseph Daniel Mallory

Stuart William Hayes

Eric W Schieve

Richard W Finch

Erik A Schuchmann

Richard Chan

Gita P Khadem

In a computer system comprising a CPU, main memory, and a memory controller, a system and method to dynamically remap memory while maintaining memory coherency. The main memory is divided into memory areas, one of which is a reserve memory area. Memory accesses are checked for errors and the errors are logged, as is the memory area in which the error occurred. The error log for each memory area is compared to an acceptable error frequency level. If a particular memory area exceeds the acceptable error frequency level, the memory area will be dynamically remapped to the reserve memory area while memory coherency is maintained. The dynamic remapping is performed by copying the memory from the memory area which exceeded the acceptable error frequency level, to the reserve memory are. During the copying, all writes to the memory area which exceeded the acceptable error frequency level are concurrently performed to both the memory area which exceeded the acceptable error frequency level and to the reserve memory area, thus preserving memory coherency. Also, the copying is performed in small blocks to avoid system timing problems.

System and method to coherently and dynamically remap an at-risk memory

A power supply system for detecting an operating configuration of a device, such as a processor, and for providing a corresponding operating voltage to the device. The power supply system includes a configurable power supply receiving configuration signals and for providing an operating voltage having a level corresponding to the configuration signals. A frequency determination circuit, such as a speed jumper block, is provided for asserting a signal indicative of the operating frequency of the device. Also, a device configuration circuit receives a signal indicative of the operating frequency and also receives a signal indicative of a plane configuration of the device, and correspondingly asserts the configuration signals to correspond to one of a matrix or plurality of predetermined operating voltage levels. A method of detecting an operating configuration of a device and for asserting a corresponding operating voltage to the device includes steps of detecting a frequency of operation, detecting a plane configuration of the device and asserting an operating voltage to the device having a level corresponding to the operation frequency and the plane configuration.

Method and apparatus for automatically detecting device specifications

The present application describes a tuned guard circuit device and method for controlling impedance levels of transmission lines on a printed circuit board having at least one ground plane and at least two circuit components coupled by a conductive transmission line. The guard circuit device of the present invention includes two etched conducting guard bands on the printed circuit board disposed on opposite sides of a selected transmission line and affixed in a spaced parallel relation to the transmission line. The guard bands are of substantially constant width and substantially constant distance from the ground plane and have substantially the same length as the transmission line, and each guard band has a first and a second terminal end. Also included is a capacitor connected to the ground plane and connected at each of the first and second terminal ends of each guard band wherein the guard bands are connected to ground through the capacitors. The guard circuit device controls the impedance level of the transmission line by varying the capacitance values of the capacitors to optimize the impedance level of the transmission line. The capacitance values of all the capacitors are, preferably, equal.

Tuned guard circuit for conductive transmission lines on a printed

A method and apparatus which enhances computer system performance in systems that incorporate a cache system that requires a first non-zero number of wait states and a memory system write buffer that requires a second lesser number of wait states. The present invention reduces or eliminates wait states that are otherwise required during write cycles in prior art designs without adding cost. During burst writes to data entries cached in the second level cache system, a cache protocol is used whereby the cache controller snoops the respective addresses which are the target of the burst write cycle out of the cache system, i.e., marks the respective cache line invalid. This effectively eliminates the data from the cache at the beginning of the burst write cycle. Since the data has now been marked invalid, the cache line is not required to be updated. Thus, the second level cache system effectively behaves as a write through cache system on these bursted writes, and the bursted writes pass through the cache system directly to the zero wait state write buffer in the memory controller. Therefore, the present invention increases system performance by reducing the write latency and thus improves the overall memory bandwidth of the processor.

Method and apparatus for reducing write cycle wait states in a non-zero

A modular computer bus providing a system for automatically maintaining proper bus termination. A module connector is located at on end of the bus. A switch device is located at the end of the bus as close as possible to the connector. The switch device couples a termination device to the end of the bus when the switch device is in an on state. The switch device is in the on state when no module is present in the connector and in an off state when a module, such as a processor module, is present in the connector. When the switch device is in the off state, the termination device is not coupled to the bus. Instead the end of the bus is terminated by a termination device on the module. Thus, computer bus is correctly terminated automatically when a module is inserted into or removed from the connector. Thus a bus structure is provided for implementing a bus standard while providing modularity and automatically maintaining proper bus termination. The superior flexibility, upgradeability and serviceability benefits of a modular bus system are achieved without incurring the increased damage risk, cost, and user confusion disadvantages of prior termination techniques.

System for automatic reconfiguration termination to multi-processor bus

There is disclosed a technique for constructing a printed circuit board assembly to provide solder joints with a uniform height. A solder mask is provided on the external surfaces of the printed circuit board to minimize the mount of conductive pad area that is exposed to solder. The solder mask includes a plurality of relatively small openings with a predetermined pattern to minimize the build up of solder, while insuring sufficient solder height to connect to the grounding component located on the chassis to insure adequate EMI protection. Preferably a polka dot pattern is used for certain conductive pads, while a single narrow strip or the solder mask opening configuration is used for rectangular pad configurations. Other configurations and patterns are also available to provide an adequate electrical connection while insuring uniform solder height.

System and method for providing uniform solder jiunt height for printed

An apparatus and method for address pipelining of a computer system that reduce the average number of wait states required to access a dynamic random access memory (DRAM) subsystem. A memory controller addresses a plurality of random access memory integrated circuits in pages of addresses wherein contiguous address pages are in different ones of the plurality of dynamic random access memory integrated circuits. Transparent latches associated with each of the different ones of the plurality of dynamic random access memory integrated circuits allow pipelining of address setups for more than one memory page at substantially the same time. The apparatus and method improve the write access times of a computer system and, when used with a computer system having address pipelining, both read and write accesses are improved because address set up latency time is reduced.

Apparatus and method for address pipelining of dynamic random access

A power supply including a detection and switch system for sensing either a uni-plane or a split-plane device connected to a socket and for providing one or two supply voltages, respectively. In one embodiment, a dual output regulator includes first and second regulators with corresponding first and second feedback circuits and comparators for regulating first and second outputs, respectively. A switch circuit connects the second feedback circuit to the comparator of the second regulator in split-plane mode for providing the second output. However, the switch circuit connects the first feedback circuit to the comparator of the second regulator in uni-plane mode where the two outputs are coupled together by a uni-plane device, so that the two outputs are regulated at the same level. A detection circuit monitors the output signals and controls the switch circuit depending upon whether a uni-plane or split-plane device is detected. The detection circuit includes a comparator which compares the output voltages, which are the same if connected to a uni-plane device or separated by a predetermined amount if connected to a split-plane device. In one regulator embodiment, the outputs are compared after reaching regulation and in a second regulator embodiment, one regulator is momentarily disabled for making the comparison while either one or both outputs voltages are increasing. In another embodiment, two separate power supplies are included for providing separate voltage levels if a split-plane device is connected, where the second power supply is disconnected if a uni-plane device is connected.

Power supply including a detection and switch system for uni-plane and

A memory write disable circuit which disables write operations to main memory during cache diagnostics and thus provides a generic means for testing cache memory systems. Disabling write operations to main memory allows the diagnostics to easily distinguish between cache hits and cache misses during diagnostics. The disable circuit operates by disabling the output enable for the main memory write signal. This disables writes to main memory in a manner external to the memory controller and thus allows tags to be loaded from a cacheable space in main memory. This enables the testing of cache memory systems in computer systems using integrated cache and memory controllers which prevent read hits to memory addresses whose cacheability has been disabled. This also provides a testability function that is hardware independent and thus can be used regardless of the configuration or processor used in the computer system.

Cache testability circuit for embedded diagnostics

An interconnect structure is provided for converting or adapting select signals sent between a printed circuit board (PCB) and an electrical component. The interconnect structure comprises an adapter card placed between the PCB and the electrical component, wherein the adapter card includes one or more pass-through vias and non pass-through vias extending completely through the adapter card in parallel spaced relation to one another. Pass-through vias are used to couple signals having critical timing paths between the electrical component and the PCB without substantially modifying or changing the critical path switch points. The pass-through vias also provide connection of signals of non critical timing between the PCB and the component. A signal converter may be used to convert non-critical signals and place those signals at select pins upon the electrical component. Thus, the adapter card is well suited for providing conversion to newer, updated components which are pin-for-pin compatible with, and which operate at dissimilar voltages from, older components. The adapter card performs all necessary signal conversion without requiring modification to the larger PCB.

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Austin, TX, United States of America

Joseph A Vivio