Intel Corporation

Other

Joseph A Schaefer

Gary A Solomon

Edward Butler

William J Chalmers

Robert A Dunstan

Kirk D Brannock

Justin J Song

David B Minturn

Andy Hoffman

Kimberly A Davis

Sunil K Mahawar

David E Mayhew

Todd Comins

Lynne Michelle Brocco

Gary L McAlpine

Robert L Huff

Brad Saunders

Oleg Awsienko

Daniel A Rich

Michael F Kartoz

Donald Hewett

Devadatta V (Deva) Bodas

Muralidhar (Murali) Rajappa

James W (Jimbo) Alexander

Prashant Sethi

Devadatta V Bodas

James W Alexander

Muralidhar Rajappa

Dave Edwards

Don G Craven

Peter I Iskiyan

A process identifier for a job is collected. The job runs on a plurality of nodes. The job is identified using the process identifier. A node for the job is identified. An amount of power consumed by the node to run the job is determined.

Profiling a job power and energy consumption for a data processing system

An indication of a mode for a job is received. An available power for the job is determined based on the mode. A first power for the job is allocated based on the available power. A first frequency for the job is determined based on the available power. The first power is adjusted based on the available power.

Power aware job scheduler and manager for a data processing system

A non-transitory computer readable storage medium having stored thereon instructions executable by one or more processors to perform operations including: receiving a plurality of input parameters including (i) a workload type, (ii) a list of selected nodes belonging to a distributed computer system, and (iii) a list of frequencies; responsive to receiving the plurality of workload parameters, retrieving calibration data from a calibration database; generating a power estimate based on the plurality of workload parameters and the calibration data; and providing the power estimate to a resource manager is shown. Alternatively, the input parameters may include (i) a workload type, (ii) a list of selected nodes belonging to a distributed computer system, and (iii) an amount of available power, wherein the estimator may provide an estimation of the frequency at which the nodes should operate to utilize as much of the available power without exceeding the available power.

Methods and apparatus to estimate power performance of a job that runs on multiple nodes of a distributed computer system

In some embodiments a detector detects a host or device coupled via a link. A port negotiates with a port of the detected host or device and determines whether to operate as a host and/or as a device. Other embodiments are described and claimed.

Universal serial bus host to host communications

In some embodiments a Universal Serial Bus cable includes a first differential pair to transmit bus signals, and a second differential pair to transmit bus signals in a same direction as the bus signals transmitted by the first differential pair. In this manner, a bandwidth of the Universal Serial Bus cable is doubled in that same direction. Other embodiments are described and claimed.

Asymmetrical serial communications

Asymmetrical universal serial bus communications

A multiple-domain processing system includes a multi-dimensional switching fabric to provide intra-domain and inter-domain communication within the system.

Multiple-domain processing system using hierarchically orthogonal switching fabric

A method for accessing a configuration space of a device is described. The method includes setting a first field of a packet to a value to specify a destination device, and setting a second field of the packet to a defined value to indicate that the packet is a configuration access packet. The method further includes setting a third field of the configuration access packet to a value to select one of a plurality of configuration apertures of a configuration space of the destination device, and setting a fourth field of the configuration access packet to a value to address a specific memory location within the selected aperture.

Configuration access mechanism for packet switching architecture

A queuing mechanism is described for managing packets between agents of a computer system. The queuing mechanism includes an ordered queue including a plurality of queue registers to store a plurality of packets. The queuing mechanism also includes a bypass queue coupled to the ordered queue, wherein, if a packet at head of the ordered queue is a delayed request and is stalled for lack of flow control credit, then the stalled packet is moved into the bypass queue.

Deadlock avoidance queuing mechanism

A switching fabric handles transactions using a protocol that directs packets based on path routing information. Components participate in transactions using a protocol that issues packets based on physical location of a destination device over the switching fabric, by establishing a virtual link partner relationship between the components.

Power management over switching fabrics

A method and an apparatus to configure a multi-port device are disclosed. The method includes defining a first set of pointers, one for each port of the multi-port device, and storing the first set of pointers in one or more capability structures of the multi-port device.

Multi-port device configuration

A system having an I/O interconnect topology utilizes internal packetized communications. The system includes a host system element, a plurality of switching elements, and a root complex to bridge communications between the host system and the switching elements. The ports of at least some of the switching elements have a cross-link device associated therewith, which is a logical device defined by configuration space of the switching element. Each cross-link device defines a cross-link communication path between two switching elements of the hierarchy allowing communications between peripherals to bypass the host.

System and method for communicating over intra-hierarchy and inter-hierarchy links

A BIOS having a set of effectors to initialize harware within the system. The BIOS having a set of macros, each macro of the set of macros having a reference to an effector of the set of effectors, each macro of the set of macros having a set of arguments.

Bios having macro/effector pairs for hardware initialization

In one embodiment, the invention is a method. The method includes receiving expected values of a configuration. The method also includes comparing the expected values with values of a configuration database. Furthermore, the method includes reporting results of the comparing.

Growing community of inventors

Beaverton, OR, United States of America

Joseph A Schaefer