Amdahl Corporation

Sun Microsystems, Inc.

Other

Joseph A Petolino

Jeffrey A Thomas

Christopher D Finan

Michael DeMar Taylor

Kevin L Daberkow

Ajay K Shah

Jeffrey T Isozaki

Michael J Begley

Daniel Carl Sobottka

Sanjay Vishin

Gary A Woffinden

Allan J Zmyslowski

Mark Semmelmeyer

Arthur T Leung

Robert M Maier

Theodore S Robinson

Richard J Tobias

James P Millar

Robert A Ertl

Shen H Wang

Nicholas Y Pang

Harold F Christensen, Jr

Emil W Brown, Iii

Harold F Christensen

Mehrzad Kasrazadeh

Jack Chen

An apparatus and method for quickly and efficiently handling mispredicted branch instructions in a computer processor having multiple instruction execution pipelines and utilizing branch delay slot instructions. When a mispredicted branch occurs, all instructions that follow the branch in execution order, including the branch delay slot instruction, die in the pipeline. The delay slot, if it is to be executed, is then reissued to the pipeline.

Fast handling of branch delay slots on mispredicted branches

Methods and apparatus for using a store allocate policy to eliminate the stale data problem in a direct mapped, write-through virtual data cache. A hardware mechanism provided by the present invention, ensures that a single cache location associated with more than one virtual address does not become stale with respect to the main memory. By using a store allocate policy along with a write-through virtual cache, each time a store miss occurs, the data cache location for which the store miss occurred will be updated with new data brought back from the main memory along with a new cache tag. The store allocate policy for a write-through virtual data cache is implemented by a data cache controller. Thus, using this cache policy, the cache is updated along with the main memory even after a store miss. Furthermore, since not more than one virtual address may exist at any one time in the cache, it is ensured that a virtual address that is found in the cache will always contain the most updated data, hence overcoming the stale data problem.

Method and apparatus for solving the stale data problem occurring in

A cache memory is arranged using write buffering circuitry. This cache memory arrangement comprises a Random Access Memory (RAM) array for memory storage operated under the control of a control circuit which receives input signals representing address information, write control signals, and write cancel signals. At least one address register buffer is coupled to the address input of the RAM, while at least one data register buffer is coupled to the data input of the RAM. Thus, in accordance with the present invention, addresses to be accessed in the RAM, as well as data to be written to the RAM, are buffered prior to being coupled to the RAM. As a result, systems utilizing the cache memory arrangement of the present invention need not stall or delay the output of information toward the RAM in order to check for a cache hit or miss. Such determinations can advantageously be made while the relevant address and data are in the register buffers en route to the RAM. Any write cancels necessitated by a cache miss then abort the write prior to the coupling of the write address and data to the RAM.

Cache memory arrangement with write buffer pipeline providing for

A computer system architecture implementing multiple central processing units, each including a split instruction and operand cache, and that provides for the management of multiple copies (line pairs) of a memory line through the use of a line pair state is described. Systematic management of memory lines when transferred with respect to instruction and operand data cache memories allows the integrity of the system to be maintained at all times. The split cache architecture management determines whether a memory line having a first predetermined system address is present within both the instruction and operand cache memories or will be upon move-in of a memory line. Address tag line pair state information is maintained to allow determinations of whether and where the respective memory line pair members reside. The architecture implements the management of the line pairs on each transfer of a memory line to any of the split caches of the system. A line pair is allowed to exist whenever the same memory line exists in the same relative location in each of the instruction and operand cache buffers of a single central processor. The architecture further includes a data path selector for transferring operand data to either the instruction or operand data cache buffers, or both, depending on whether the operand buffer destination is a memory line that is a member of a line pair.

Computer system architecture implementing split instruction and operand

An apparatus and method for use in improving cache storage unit utilization during an interlock of an instruction pipeline generates a control signal during one cycle of the interlock if the interlocked instruction may require storage unit management work. In response to the control signal, selector control logic in the storage unit generates a priority signal indicating the interlocked instruction for selection by the storage unit for processing. In response to the control signal and the priority signal, the cache management logic is used during the interlock on the interlocked instruction to prepare for supplying needed data when the interlock is released.

Apparatus and method for improving cache access throughput in pipelined

In a data processing system including a pipelined instruction execution unit and a pipelined high speed cache, a storage queue consisting of a set of FIFO registers and associated support logic handles transfer of data from the pipeline instruction execution unit to the high speed cache. When a store request flow from the instruction execution pipeline is forwarded to the high speed cache, instead of placing the data directly into the high speed cache, the starting address, length of store and data to be stored are placed into one of the store queue registers. The instruction execution unit sees the store request as completed and continues processing even though data has not been physically placed in the high speed cache. The write to the high speed cache is finished in the background at a later time during an unused storage pipeline cycle in the high speed cache.

Monolithic semi-custom IC having standard LSI sections and coupling gate

In a pipeline data processing machine having a first unit for execution of instructions running according to a first pipeline and a second unit for storing data from a plurality of ports running according to a second pipeline, the first unit having a result register for holding results including data and address information of a flow of the first pipeline, the present invention provides an apparatus for transferring results in the result register to the second unit. A plurality of registers connected to the result register, each storing the result from at least one flow of the first pipeline and storing control information is provided. Further, a controller in communication with the second unit and the plurality of ports responsive to the control information and a flow of the second pipeline is included for selecting one of the plurality of ports in a first-in, first-out queue as a port to the second unit and for updating the control information.

Cache storage queue

Bypassing of data from a main storage unit to an instruction and operand processing unit around an intermediate storage unit improves performance in a data processing system. The instruction and operand processing unit supplies requests for operands to the intermediate storage unit or cache. If the line is missing from the cache, the request operand is retrieved from the main storage unit. A bypass data path is connected between the main storage unit, prior to error detecting means in the cache, and the instruction and operand processing unit for transferring requested operands to the instruction and operand processing unit directly. Control, coupled to receive requests for operands and to the instruction and operand processing unit, signals the instruction and operand processing unit to receive the requested operands from the bypass data path when the data includes a requested operand.

Cache move-in bypass

The present invention provides an apparatus for reporting errors in data stored in a memory apparatus of a data processor, comprising: first means for storing multiple digital first signals; second means for storing said multiple digital first signals and adapted for storing at least one digital second signal; third means for transmitting said multiple digital first signals substantially from said first means to said second means; fourth means for providing said at least one digital second signal, in the course of the transmitting of said first signals by said third means, in response to an occurrence of one or more errors in one or more of said multiple digital first signals; fifth means for transmitting said multiple digital first signals substantially from said second means to said first means; and sixth means adapted for receiving said at least one digital second signal in the course of the transmitting of said multiple digital first signals by said fifth means and for providing at least one third signal in response to an occurrence of said at least one digital second signal. ECC codes are generated and applied over a plurality of distinct checking blocks in each flow of data in order to minimize delays in the move-in data path, and bypass data paths are provided such that a flow may bypass all error checking and correcting circuitry and cacheing apparatus between the main storage array and the CPU.

Error detection and correction scheme for main storage unit

A system for updating an ECC code over a line in a data store when only part of the line has been updated is described. The system receives the update and its address, decodes the address to generate a first signal identifying the part of the line to be updated and a second signal identifying an un-updated part of the section. The data of the update and the first signal are used to generate a first partial error code. Data from the un-updated part of the line is read as the update is written to the store. The data from the un-updated part of the section and the second signal are used to generate a second partial error code. Finally, the first and second partial error codes are combined to generate the updated error code.

Cache error code update

The present invention provides an apparatus for reporting errors in data stored in a memory apparatus of a data processor, comprising: first circuitry for storing multiple digital first signals; second circuitry for storing the multiple digital first signals and adapted for storing at least one digital second signal; third circuitry for transmitting the multiple digital first signals substantially from the first circuitry to the second circuitry; fourth circuitry for providing the at least one digital second signal, in the course of the transmitting of the first signals by the third circuitry, in response to an occurrence of one or more errors in one or more of the multiple digital first signals; fifth circuitry for transmitting the multiple digital first signals substantially from the second circuitry to the first means; and sixth circuitry adapted for receiving the at least one digital second signal in the course of the transmitting of the multiple digital first signals by the fifth circuitry and for providing at least one third signal in response to an occurrence of the at least one digital second signal.

Apparatus and method for reporting occurrences of errors in signals

A data processing machine includes an instruction unit that decodes and organizes a flow of instructions for processing data. In response to certain instructions, the instruction unit generates requests for storage unit resources. In addition, results generated in the instruction unit in response to certain instructions are supplied for storage in the storage unit. The storage unit selects in response to priority logic from completing requests for storage unit resources, including a high speed cache storing data, and a plurality of storage ports for transferring data from the result register to the high speed cache. Each of the storage ports generates requests for access to the high speed cache to transfer the data stored in the respective store ports to the cache. Storage unit priority is determined in part by predicting the fullness of the storage ports.

Growing community of inventors

Palo Alto, CA, United States of America

Joseph A Petolino