Northrop Grumman Systems Corporation

Joseph A Payne

Silai V Krishnaswamy

Jeffrey David Hartman

Jonathan D Egan

Wayne Stephen Miller

Monica P Lilly

Jeffrey S Hall

One example includes a superconducting circuit chip. The chip includes superconducting circuitry that operates based on a clock signal. The chip also includes a ring oscillator configured to receive a synchronization signal from a ring oscillator associated with another superconducting circuit chip. The ring oscillator is also configured to provide a trigger signal to the superconducting circuitry at a given phase of the clock signal relative to a phase of the clock signal of a trigger signal associated with the other one of the superconducting circuit chips based on the synchronization signal.

Superconducting circuit multi-chip synchronization system

A radio-frequency (RF) carbon-nanotube (CNT) field effect transistor (FET) device. The device includes a source contact, a drain contact, semi-conducting CNTs positioned between the source and drain contacts, high-&#x3ba; gate dielectric, and a local backgate positioned below the semi-conducting CNTs, in which the local backgate is capable of RF performance and is capable of being used in a backgate burnout process used to enhance the semiconducting to metallic tube ratio of the device.

Radio-frequency carbon-nanotube field effect transistor devices with local backgates and methods for making same

Embodiments of a method and apparatus for removing metallic nanotubes without transferring CNTs from one substrate to another substrate provide two methods of transferring a thin layer of crystalline ST-cut quartz wafer to the surface of a carrier silicon wafer for subsequent CNT growth, without resorting to CNT transfer. In other words, embodiments of a method and apparatus allow CNTs to be grown on the same substrate that metallic nanotube removal is performed, therefore eliminating the costly and messy step of transferring CNTs from one substrate to another. This is achieved through a residual thin layer of crystalline ST-cut quartz layer on a silicon wafer. The ST-cut quartz wafer promotes aligned growth of CNTs, while the underlying silicon wafer allows backgate burnout.

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Elkridge, MD, United States of America

Joseph A Payne