Intel Corporation

Lsi Corporation

Agere Systems Inc.

Avago Technologies General IP (singapore) Pte. Ltd.

Joseph A Manzella

Walter A Roper

Nilesh S Vora

Ritchie J Peachey

William G Burroughs

Deepak Mital

Robert J Munoz

Zhong Guo

David Sonnier

Robert H Leonowich

Matthew Tota

Jack Lee

John Leshchuk

Michael T Mangione

Edmond H Barakat

An network processor is described that is configured to multicast multiple data packets to one or more engines. In one or more implementations, the network processor includes an input/output adapter configured to parse a plurality of tasks. The input/output adapter includes a multicast module configured to determine a reference count value based upon a maximum multicast value of the plurality of tasks. The input/output adapter is also configured to set a reference count decrement value within the control data portion of the plurality of tasks. The reference count decrement value is based upon the maximum multicast value. The input/output adapter is also configured to decrement the reference count value by a corresponding reference count decrement value upon receiving an indication from an engine.

Network processor having multicasting protocol

Described embodiments process data packets received that include a source address and at least one destination address. If the destination address is stored in a memory of an I/O adapter, the received data packet is processed in accordance with bridging rules associated with each destination address stored in the I/O adapter memory. If the destination address is not stored in the I/O adapter memory, the I/O adapter sends a task message to a processor to determine whether the destination address is stored in an address table stored in a shared memory of the network processor. The I/O adapter memory has lower access latency than the address table. If the destination address is stored in the address table, the received data packet is processed in accordance with bridging rules stored in the address table and the bridging rules stored in the I/O adapter memory are updated.

Address learning and aging for network bridging in a network processor

Described embodiments provide a method of operating a network processor coupled to a network via a communication link. An input/output adapter receives a data packet. A classification module provides control values of the data packet to a statistics module. The statistics module determines (i) updatable statistics based on the control values, and (ii) an address of a statistics bin in a memory of the network processor corresponding to the statistics. Updated values of the statistics are stored at the corresponding address. Values at selected addresses are processed by a control processor of the network processor, generating traffic characteristics for the data packets. The control processor adjusts operation of the network processor based on the traffic characteristics.

Statistics module for network processors in virtual local area networks

An apparatus having a parser and a circuit is disclosed. The parser is configured to generate a source address, a destination address and information by parsing a packet received via one of a plurality of networks. The circuit is configured to search a plurality of memories in parallel during a single cycle of operation in the apparatus. The searching includes a plurality of lookups in the memories of a plurality of data sets associated with the source address, the destination address and the information, respectively. The circuit is also configured to bridge the packet between the networks in response to the data sets.

High speed network bridging

Described embodiments provide a system having at least two network processors that each have a plurality of processing modules. The processing modules process a packet in a task pipeline by transmitting task messages to other processing modules on a task ring, the task messages related to desired processing of the packet. A series of tasks within a network processor may result in no processing or reduced processing for certain processing modules creating a virtual pipeline depending on the packet received by the network processor. At least two of the network processors communicate tasks. This communication allows ter the extension of the virtual pipeline of or IC network processor to at least two network processors.

Sharing of internal pipeline resources of a network processor with external devices

An apparatus for supporting multicast address learning in a network processor includes a task parameter decoder receiving the packet and determining parameters of the packet, a plurality of unlearned address counters recording a number of the packets to be multicast, a correlator determining destination addresses of the packet, a multicast replicator replicating the packet multiple times, and a task generator generating a generated packet with a bitmap and sending out the generated packet to an I/O adaptor over a task ring interface of the network processor. If the packet is unlearned, the unlearned address counter is then incremented and the unlearned packet is sent back to a special queue in the I/O adaptor over the task ring interface with an index to the bitmap for replicating by the multicast replicator, after replicating, the unlearned address counter is decremented. Methods for replicating unlearned/learned multicast packets within a network processor are included.

Multicast address learning in an input/output adapter of a network processor

In described embodiments, a timestamp generator includes a fixed clock domain driven by a fixed frequency clock, a core clock domain, coupled to the fixed clock domain, which is driven by a core clock whose frequency is adjustable during an operation of the timestamp generator. A timestamp logic operating in the core clock domain generates a timestamping output of the timestamp generator. A rate generator operating in both the fixed clock domain and the core clock domain generates per clock cycle increments in the fixed clock domain and transfers carry units from the fixed clock domain into the core clock domain, and a timestamp increment generation of the timestamp logic is clocked by the fixed frequency clock provided by the rate generator. A method for enabling timestamp in an ASIC to be accurate with system clock changes is also described.

Timestamping logic with auto-adjust for varying system frequencies

A scalable packet switch possessing a multiport memory, a multiport memory manager, two or more input/output (I/O) ports, and two or more switch engines. Each switch engine is associated with one or more I/O ports, and is adapted to receive inbound packets and transmit outbound packets via the associated I/O ports. Inbound packets are stored in a shared packet buffer. Each switch engine is further adapted to (i) determine (i.e., bridge) the outbound I/O port(s) for received inbound packets by consulting a shared bridging table and (ii) schedule outbound packets for transmission, independently and in parallel with other switch engines. The shared packet buffer and shared bridging table are stored in the multiport memory and shared by all switch engines. The multiport memory manager allocates/de-allocates memory blocks within the multiport memory.

Scalable packet-switch

An auto-detection system and method for a network transceiver that allows the network transceiver to switch from a first rate mode to a second rate mode automatically. In one embodiment, the system includes: (1) an error counter, coupled to a receive input of the network transceiver, that accumulates a count of code violations while the network transceiver is operating in the first rate mode and (2) mode-switching circuitry, coupled to the error counter, that switches the network transceiver to the second rate mode when the count reaches a predetermined value.

Auto-detection system and method for a network transceiver

A multi-port Ethernet device having a MUX mode passing internal status signals (e.g., ACT, LINK, SPEED, FDUP, CS, TPJS, TPAPS, RS, and/or XS) for each of a plurality of Ethernet ports in parallel over a common set of external pins. The Ethernet device may be 'fixed' in a multiplexed mode such that the MUX mode is the only way in which internal status signals for each Ethernet port is transmitted external to the Ethernet device, or the Ethernet device may provide a MUX mode for status signal output in addition to otherwise conventional output modes (e.g., a parallel status signal output mode and/or a serial status signal output mode). In MUX mode, all desired internal status signals (e.g., all nine (9) standard Ethernet status signals) are time division multiplexed onto the common set of external pins one Ethernet port at a time.

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Macungie, PA, United States of America

Joseph A Manzella