Texas Instruments Corporation

Other

Joseph A Devore

Ross Eliot Teggatz

David John Baldwin

John H Carpenter, Jr

Andrew Marshall

Taylor R Efland

Thomas A Schmidt

Michael C Smayling

Satwinder S Malhi

Eric Christian Blackall

Alec James Morton

Tohru Tanaka

R Travis Summerlin

Wayne T Chen

Jonathan S Brodsky

Timothy Patrick Pauletti

Robert Steinhoff

Toru Tanaka

Stephen C Kwan

Ricky Dale Jordanger

William E Grose

Konrad Wagensohner

Wayne Tien-Feng Chen

Benjamin Lee Amey

Kenneth G Buss

Reed Wilburn Adams

Brett Jason Thompsen

Rex M Teggatz

Timothy John Legat

Zhihong You

Ross Elliot Teggatz

Stephen L Sutton

Jonathan R Knight

Raymond T Summerlin

Ganapathy R Subramaniam

Christopher M Cooper

Systems, methods and circuits for regulator minimum load control. In one particular case, a system is provided that includes a load control circuit and a switched load. The load control circuit includes a reference current, and a sense current representative of a load current. In addition, the load control circuit includes a comparator circuit that drives a control signal in response to a comparison between the reference current and the sense current. The switched load is electrically coupled to a load voltage signal to provide loading to the load voltage signal. The switched load is operable to switch between a first loading factor and a second loading factor in response to the control signal.

Circuits, devices and methods for regulator minimum load control

A method evaluating threshold of a data cell in a memory device including a programming locus coupled with the data cell for receiving a programming signal setting a stored signal level in the data cell and responding to a read signal to indicate the stored signal at a read locus; includes the steps of: (a) in no particular order; (1) selecting a test threshold signal; and (2) setting a read signal at a non-read level; (b) applying the test threshold signal to the programming locus; (c) cycling the read signal between a read level and a non-read level while applying the test threshold signal to the programming locus to present at least two test signals at the read locus when the read signal is at the read level; and (d) while cycling, observing whether the at least two test signals manifest a difference greater than a predetermined amount.

Method evaluating threshold level of a data cell in a memory device

A method evaluating threshold of a data cell in a memory device including a programming locus coupled with the data cell for receiving a programming signal setting a stored signal level in the data cell and responding to a read signal to indicate the stored signal at a read locus; includes the steps of: (a) in no particular order: (1) selecting a test threshold signal; and (2) setting a read signal at a non-read level; (b) applying the test threshold signal to the programming locus; (c) cycling the read signal between a read level and a non-read level while applying the test threshold signal to the programming locus to present at least two test signals at the read locus when the read signal is at the read level; and (d) while cycling, observing whether the at least two test signals manifest a difference greater than a predetermined amount.

System and method for controlling current across a load. A preferred embodiment comprises a current varying circuit (such as current varying circuit) that can create a sequence of voltage drops in a driver circuit (such as the driver circuit) coupled to an inductive load (such as the inductive load). By initially producing a large voltage drop and then stepping the voltage drop down gradually, the current in the inductive load can be rapidly removed without producing a current undershoot, which, in certain applications, can result in unwanted noise and vibration.

Current control via a variable voltage snubbing network

The present invention includes a MOS device () that has a P-type substrate () and an N-type drain region () formed within the substrate (). An annular N-type source region () generally surrounds the drain region (). The source region () serves as both the source for the MOS device () and a sacrificial collector guard ring for an electrostatic discharge protection circuit. An annular gate region () generally surrounds the drain region () and is electrically insulated from the drain region () and electrically connected to the source region (). An annular P-type bulk region () generally surrounds the source region () and is electrically connected to the source region ().

MOS ESD CDM clamp with integral substrate injection guardring and method for fabrication

A high-breakdown voltage transistor ( ) is disclosed. The transistor ( ) is formed into a well arrangement in which a shallow, heavily doped, well ( ) is disposed at least partially within a deeper, more lightly-doped well ( ), both formed into an epitaxial layer ( ) of the substrate ( ). The deep well ( ) is also used, by itself, for the formation of high-voltage transistors, while the shallower well ( ) is used by itself in low-voltage, high-performance transistors. This construction permits the use of high-performance, and precisely matching, transistors in high bias voltage applications, without fear of body-to-substrate (or &ldquo;back-gate-to-substrate&rdquo;) junction breakdown.

Method for making low voltage transistors with increased breakdown voltage to substrate having three different MOS transistors

One aspect of the invention is an integrated circuit ( or ) comprising an amplifier ( or ) having at least two poles in its frequency response and an output impedance compensation circuit (M A, M M AC or M A, M M M AC ) coupled to an output node ( ) of the amplifier ( or ). The output impedance compensation circuit (M A, M M AC or M A, M M M AC ) is operable to create a feedback signal proportional to the impedance of an output load ( ) coupled to the output node ( ), and create a zero in the frequency response of the amplifier ( or ) in response to the feedback signal between the at least two poles.

Method and system for dynamic compensation

A circuit and method are provided for accurate and adjustable current limiting/sensing in a power IC ( ). In particular, a current limiting/sensing circuit ( ) and method of use are provided that substitutes a transistor (MD ) in place of a resistor. Consequently, all of the components (MD , MD , MD ) in the IC ( ) may be identical transistors, which may be fabricated by one process and integrated in one power structure. Therefore, process variations from device to device and errors due to thermal gradients between components may be minimized, thereby reducing the complexity and fabrication costs of the power ICs. Additionally, a user may readily adjust the trip/sensing point of the current limiting circuit ( ) without having to physically alter individual components in the IC ( ).

Adjustable current limiting/sensing circuitry and method

An integrated circuit ( ) having at least one programmable fuse (F ) and ESD circuitry (MN , MN ) preventing the fuse (F ) from being unintentionally blown when a voltage transient exists on a main voltage potential (V ). The ESD circuitry preferably comprises of MOSFET switches which are coupled to turn on quicker than a main fuse programming switch (MN ) due to the voltage transient, thereby insuring that the main switch remains off during the voltage transient to prevent the unintentional blowing of the fuse F The circuit is well suited for programmable logic device (PLDs), allowing for read voltages as low as 6 volts, and allowing for programming voltages as high as 40 volts.

Internal protection circuit and method for on chip programmable poly fuses

Provided is a symmetrical filter that uses a single comparator. In addition to a voltage divider, a current regulator, and a comparator, the filter of the invention provides control logic that turns on or off a pull up switch and/or pull down switch in order to fully charge or fully discharge a capacitor. Accordingly, in one aspect, the invention is a control logic for a symmetrical filter. Furthermore, timing logic is provided to provide for a more rigorous symmetrical filter performance.

Analog filtering with symmetrical timing using a single comparator

A high-breakdown voltage transistor ( &prime;) is disclosed. The transistor ( &prime;) is formed into a well arrangement in which a shallow, heavily doped, well ( ) is disposed at least partially within a deeper, more lightly-doped well ( ), both formed into an epitaxial layer ( ) of the substrate ( ). The deep well ( ) is also used, by itself, for the formation of high-voltage transistors, while the shallower well ( ) is used by itself in low-voltage, high-performance transistors. This construction permits the use of high-performance, and precisely matching, transistors in high bias voltage applications, without fear of body-to-substrate (or &ldquo;back-gate-to-substrate&rdquo;) junction breakdown.

Low voltage transistors with increased breakdown voltage to substrate

An EEPROM cell ( ) formed on a substrate ( ) using conventional process steps is provided. The cell ( ) includes first ( ) and second ( ) conductive regions in the substrate ( ) below the substrate's outer surface ( ), and the first ( ) and second ( ) conductive regions are laterally displaced from one another by a predetermined distance ( ). The cell ( ) also includes an insulating layer ( ) outwardly from the outer surface ( ) of the substrate ( ) positioned so that its edges are substantially in alignment between the first ( ) and second ( ) conductive regions. The cell ( ) further includes a floating gate layer ( ) outwardly from the insulating layer ( ) and in substantially the same shape as the insulating layer ( ). The cell ( ) also includes a diffusion region ( or ) that extends laterally from at least one of the first ( ) and second ( ) conductive regions so as to overlap with the insulating layer ( ). The diffusion region ( or ) provides a source of charge for placement on the floating gate layer ( ) when programming the EEPROM cell ( ).

EEPROM cell using conventional process steps

An integrated circuit ( ) is disclosed comprising a fundamental frequency oscillator comprising a reference node ( ) whose voltage varies between a high threshold and a low threshold. The fundamental frequency oscillator is operable to generate a first output at the fundamental frequency on a first output node ( ). The integrated circuit ( ) also comprises a circuit (C ) coupled to the reference node. The circuit (C ) is operable to sense the voltage at the reference node ( ), to determine when the voltage exceeds an intermediate threshold between the high threshold and the low threshold, and to generate a second output in response to the determination. The integrated circuit ( ) also comprises logic ( ) coupled to the circuit (C ) and load circuitry ( ) coupled to the logic ( ). The logic ( ) is operable to generate an output signal at an output frequency greater than the fundamental frequency in response to the second output and the first output.

Oscillator and method

A controlled area network (CAN) driver provides improved symmetry between its differential output signals CAN-H and CAN-L, and provides protection for its low voltage devices from voltage transients occurring on its output lines. A plurality of CAN drivers,are serially interconnected to form a driver system, wherein each downstream driver stage receives a time-delayed form of the digital input signal TxD, each stage providing a time-delayed contribution to the differential output signals of the overall driver system.

Driver for controller area network

A voltage level shifting circuit (,) and method for accomplishing a voltage level change includes a voltage level shifting circuit (,) to change an input voltage to a shifted voltage level. A second stage (,) is connected between a voltage source at the shifted voltage level (,) and the reference potential. The second stage (,) includes active devices (,) that are controlled by the voltage level shifting circuit (,). The second stage (,) also includes slope resistors (,) connected in series between the active devices (,) of the second stage (,).

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Richardson, TX, United States of America

Joseph A Devore