Texas Instruments Corporation

Spectrum Digital Incorporated

Joseph A Coomes

Gary L Swoboda

Jerald G Leach

Martin D Daniels

Laurence Ray Simar, Jr

Henry R Hoar

Chein C Chen

David E Francis

Steve P Marshall

John C Cooper

An electronic system includes electronic circuitry to be tested having serial scan shift register latches, and a serial scan generator embedded in the electronic system upon manufacture and connected to the serial scan shift register latches of the electronic circuitry to facilitate testing. The electronic system may consist of a single printed circuit board mounting both the electronic circuitry and the serial scan generator. The electronic system may consist of a single semiconductor chip carrier mounting both the electronic circuitry and the serial scan generator, are both mounted on said single semiconductor chip carrier. The electronic system may further include a detachable second serial scan generator. The serial scan generator preferably operates slower than the detachable second serial scan generator. The electronic system may further include a disabling terminal disabling the serial scan generator upon attachment of the detachable second serial scan generator.

Electronic systems testing employing embedded serial scan generator

An emulation device including a serial scan testability interface having at least first and second scan paths, and state machine circuitry connected and responsive to said second scan path generally operable for emulation control.

Integrated circuit with emulation register in JTAG JAP

An emulation device including a serial scan testability interface having at least first and second scan paths, and state machine circuitry connected and responsive to said second scan path generally operable for emulation control of logical circuitry associated with said emulation device.

Emulation devices, systems and methods utilizing state machines

An apparatus for emulating, testing, interrogating, debugging, and programming an integrated circuit is provided. The apparatus has a boundary scan adapter in association with a host computer for accepting a control signal from the host computer, and for generating an intermediate signal for acceptance by the integrated circuit which intermediate signal is compliant with the specifications of the integrated circuit. Also, the apparatus has an interface associated with the integrated circuit for accepting the intermediate signal from the boundary scan adapter. The control signal from the host computer has a magnitude greater than the magnitude of the intermediate signal which intermediate signal is specific to and compliant with the operation of the integrated circuit.

Adjustable voltage boundary scan adapter for emulation and test

A memory interface unit capable of coupling a microprocessor to memory external to the microprocessor, wherein the memory can be of at least two types differing in width, and where the data stored in such memory can be in different sizes, and wherein the memory can be formed in sections. The invention utilizes means for controlling at least two strobe signal lines and means for shifting the memory address lines, programmably, so as to accommodate the various combinations of memory width and data size.

Memory interface with address shift for different memory types

A memory interface unit for coupling a microprocessor to a memory external to the microprocessor, the memory being utilized for the storage of data therein and the retrieval of data therefrom, and the memory being provided in one or more memory banks, each of the banks being provided with a set of address lines and a byte enable line, data being transferring to and from each of the memory banks on a group of data lines, and the memory banks being provided in one or more banks whereby the group or groups of data lines, as the case may be, provide a memory data path having a physical transfer width for transfer of data to and from the memory, and the data being stored and retrieved over the memory data path in two or more data types, each type having a different size, the memory interface unit being provided with a set of address pins and a set of strobe pins, comprising. The unit includes a first element for providing an indication of a physical transfer width of a memory coupled to the memory interface unit. Also provided is a second element for providing an indication of a data type to be transferred to or from the memory. A third element, responsive to the first element and the second element, depending on the data type indication, provides to the address pins an address, shifted in position, with at least some of the address lines being for coupling to the address lines of the one or more banks of memory, as the case may be, and with one or more of the address pins being for activation of the byte enable line or lines, as the case may be, for data to be transferred, or, alternatively, providing to the address pins an address, unshifted in position, for coupling to the address lines of the one or more banks of memory, as the case may be, for addressing data to be transferred. Depending on the physical transfer width indication, the third element also causes one or more of the strobe pins to be used as additional address pins.

Programmable memory interface for efficient transfer of different size

An electronic system for use with a host computer. The system includes electronic circuitry including a first semiconductor chip generally operable for a first function and also adapted for input and output of emulation signals. This is combined with emulation circuitry including a second semiconductor chip adapted for connection to the host computer. The emulation circuitry is connected to the electronic circuitry to generate emulation signals to input to the electronic circuitry and to accept emulation signals from the electronic circuitry. A physical assembly supports the emulation circuitry and the electronic circuitry as a unit. Other electronic systems and emulation and testing devices, cables, systems and methods are also disclosed.

Electronic systems and emulation and testing devices, cables, systems

A data processing device comprising a clock generator for producing pulses establishing instruction cycles, a memory accessible by assertion of addresses, an instruction decode and control unit, having an instruction register operative to hold a program instruction, operative to decode a program instruction providing control signals according to a pipeline organization to control the operations of the data processing device within each instruction cycle and to initiate a block sequence responsive to an instruction code representing a block instruction. A program sequencer circuit, having a program register to hold a program count corresponding to a program address, is operative to access the memory with the contents of the program register to obtain the program instruction corresponding to the program address. Further included is an arithmetic logic unit operative to perform an arithmetic operation on data received by the arithmetic unit and to combine the contents of the program register with a data field decoded from the block instruction by the instruction decode and control unit to generate a block end address, and a block handler unit, having a block start register operative to store the contents of the program register, is responsive to the control signals from the instruction decode and control unit to store the program address corresponding to the block start address to the block start register wherein the contents of the block start register correspond to a start address for a block of instructions to be executed. Other devices, systems and methods are also disclosed.

Growing community of inventors

Missouri City, TX, United States of America

Joseph A Coomes