Gte Communication Systems Corporation

Ag Communication Systems Corporation

Joseph A Conforti

Anthony J Baca

Thomas C Bissonnette

A digital line card for interfacing a remotely located digital telephone to a central office system by a two-wire connection is disclosed. The digital line card consists of a line interface connected to the two-wire connection. The line interface provides a full duplex transmission link with the remotely located digital telephone over the two-wire connection. A buffer is connected between the line interface and the central office system. The buffer converts data between the line interface and the central office system. The line card further comprising a protocol controller connected to the line interface. The protocol controller performs a packet protocol for communications with the remotely located telephone. To complete the line card, there is provided a processor connected to the protocol controller and to the central office system, under the direction of the central office system, the processor controls the operation of the digital line card and, through the protocol controller means, communicates with and controls the remotely located digital telephone.

Digital line card for interfacing a remotely located digital telephone

A digital test card for testing the quality of a digital system in a central office system is disclosed. Where the digital system consists of a digital line card connected to a customer premise equipment by a two-wire connection. The digital test card comprises a line interface which provides a full duplex transmission link. When the digital test card is testing the customer premises equipment the line interface operates as a master; when testing the digital line card the line interface operates as a slave. There is also a relay for connecting the line interface to the customer premise equipment or the digital line card. Connected between the line interface and the central office system is a buffer. A protocol controller connected to the line interface performs a packet protocol. And finally there is a processor. Under the direction of the central office system, the processor controls the operation of the digital line card and determines the quality of the digital system.

Circuit for testing digital lines

This circuitry permits equal access to a shared resource by a number of central processing units (CPUs). In a multiple CPU arrangement, common resource contention problems arise, when several CPUs attempt to access the common resource. To resolve these contention problems, this circuitry is an improvement to arbitration ring circuitry. The circuitry of this invention permits each of the CPUs equal access to the common resource during situations in which each CPU is constantly generating requests (high bandwith utilization) for access to the common resource. This invention is particularly useful for systems in which a large number of CPUs must have their local memory rapidly reloaded from a common memory source. Reloading procedures for large numbers of CPUs require up to an hour. By employing the present invention, these reloading times can be cut from one hour to approximately 5 minutes.

Increased bandwith for multi-processor access of a common resource

This circuitry permits equal access to a shared resource by a number of central processing units (CPUs). In a multiple CPU arrangement, common resource contention problems arise, when several CPUs attempt to access the common resource. To resolve these contention problems, this circuitry is an improvement to arbitration ring circuitry. The circuitry of this invention permits each of the CPUs equal access to the common resource during situations in which each CPU is constantly generating requests (high bandwidth utilization) for access to the common resource. This invention is particularly useful for systems in which a large number of CPUs must have their local memory rapidly reloaded from a common memory source. Reloading procedures for large numbers of CPUs rquire up to an hour. By employing the present invention, these reloading times can be cut from one hour to approximately 5 minutes.

Increased bandwidth for multi-processor access of a common resource

This circuitry permits equal access to a shared resource by a number of central processing units (CPUs). In a multiple CPU arrangement, common resource contention problems arise, when several CPUs attempt to access the common resource. To resolve these contention problems, this circuitry is an improvement to arbitration ring circuitry. The circuitry of this invention permits each of the CPUs equal access to the common resource during situations in which each CPU is constantly generating requests (high bandwidth utilization) for access to the common resource. This invention is particularly useful for systems in which a large number of CPUs must have their local memory rapidly reloaded from a common memory source. Reloading procedures for large numbers of CPUs require up to an hour. By employing the present invention, these reloading times can be cut from one hour to approximately 5 minutes.

Simplified CCIS (Common Channel Interoffice Signalling) data transfer circuitry is shown for transmitting data between a CCIS central processing unit of a central switching office and a number of terminal equipment controllers, each having a local CPU. The terminal equipment controller operates such equipment as modems of various speed, digital trunks or T1 spans. This design minimizes the amount of circuitry required to transmit CCIS data between central processing units, thereby permitting a more reliable design. This circuit provides a minimal amount of logic required for interprocessor communication. In addition, this circuit minimizes the amount of real time required by each CPU to perform the CCIS data transfer.

Circuit for CCIS data transfer between a CPU and a plurality of terminal

This circuit provides for synchronizing duplex copies of processor controllers. Either controller may be active in the simplex mode. That is, one controller is actively operating and controlling processors, while the other controller is in a standby mode. In this situation, the synchronization circuit synchronize its clock to itself. When a previously standby controller is made active, the control inputs of the standby controller are manipulated such that, the clock of the standby controller is synchronized to the already active a controller's clock. Once synchronism is achieved, the controllers are said to be operating in a synchronized duplex mode. The synchronization circuit of each controller then continuously checks to insure that the two controller copies are operating synchronously. If a non-synchronous condition is encountered by one of the synchronization circuits, the circuit that detected the lack of synchronization is repeatedly forced to a particular memory location. After a short time interval, the opposite synchronization circuit will eventually be at this same location and synchronous duplex operation will again result.

Duplex controller synchronization circuit for processors which utilizes

Common channel interoffice data transfer circuitry is shown for transmitting and receiving both analog and digital CCIS data. This data transfer circuitry is a data terminal equipment control circuit. The terminal equipment control circuit is microprocessor controlled. The terminal equipment control circuit is adaptable to transfer CCIS data to analog interfaces, such as modems. The circuit is also adaptable to transfer CCIS data to and from digital data sources, such as digital trunks or T1 spans. The design of this circuit possesses a high degree of commonality and, therefore, requires a minimal amount of components.

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Phoenix, AZ, United States of America

Joseph A Conforti