Eaton Corporation

Cutler-hammer, Inc.

Ail Systems, Inc.

Other

Joseph A Calviello

Paul R Bie

Grayce A Hickman

John A Pierro

Ronald J Pomian

David Ward

Integrated circuit structure and processing is provided for a high power limiter including at least a first anti-parallel array of monolithically integrated Schottky diodes. In a further embodiment, integrated circuit structure and processing is provided for an MMIC, microwave and millimeter wave monolithic integrated circuit, including an amplifier and a high power limiter monolithically integrated on the same substrate.

Method of forming integrated limiter and amplifying devices

A semiconductor device and processing technique is provided for monolithic integration of a single crystal compound element semiconductor on a ceramic substrate. A high resistivity semi-insulating buffer layer is epitaxially grown on the ceramic substrate and has an elastically transitional lattice constant matching at its lower surface the lattice constant of the ceramic substrate, and matching at its upper surface the lattice constant of the semiconductor layer.

Method of making a monolithic integrated circuit having compound

Integrated limiter and amplifying devices

Monolithic integrated circuit having compound semiconductor layer

Semiconductor processing techniques and devices are provided using a partially opaque ion implantation mask to control the profile of active layers in microwave and millimeter wave monolithic integrated circuits. An N+ layer can be implanted before or after active layer formation. Selection of mask thickness enables control of active channel depth. Adjustment of gate to drain separation in MMIC FETs is also enabled, to control gate to drain voltage. Source to gate series resistance is also controlled. Multiple dielectric layers afford variable mask thicknesses to enable simultaneous formation of differing power level devices monolithically in the same substrate, including low noise high speed devices and power devices. The process and device structure provides enhanced yield, performance, uniformity and reliability.

Ion implantation masking method and devices

Method of making an FET by ion implantation through a partially opaque

A semiconductor chip (14) is bonded to a substrate (16) by a metallic molecular bond interface (28, 38, 30). The chip and the substrate are separated by a gap (18), and a metal-bearing gas is introduced in the gap. A thermal energy source (22) directs a focused energy beam (24) into the gap to thermally decompose the gas by chemical vapor reaction to deposit and grow metal to provide a metallic molecular bond interface filling the gap and bonding the chip to the substrate. In the preferred embodiment, one of the chip and substrate has a passband passing the wavelength of the focused beam to be transparent thereto such that the beam passes therethrough and into the gap and against the other of the chip and the substrate.

Low temperature semiconductor bonding process with chemical vapor

A buried channel field effect transistor is provided by in situ growth of all epitaxial layers growing laterally towards each other along central amorphous semi-insulating humps (1222, 1224) and merging (1232) above the humps to epitaxially grow in single crystalline form to provide the active N layer (1232).

Buried channel FET with lateral growth over amorphous region

On a semiconductor substrate (14, 38) T-type undercut electrical contact structure (12, 36) and methodology provides a diffusion barrier (26, 40) preventing migration therethrough from a gold layer (30, 48) along the sides of an undercut schottky metal lower layer (28, 44) into the active region of the semiconductor substrate. In one embodiment, the diffusion barrier (26) is provided at the base of the gold layer (30). In another embodiment, the gold layer (48) is encapsulated by the diffusion barrier (40) on the bottom (46) and sides (56). The diffusion barrier base layer is deposited. The diffusion barrier side layers are electroplated.

T-type undercut electrical contact on a semiconductor substrate

On a semiconductor substrate (38) T-type undercut electrical contact structure (12, 36) and methodology provides a diffusion barrier (26, 40) preventing migration therethrough from a gold layer (30, 48) along the sides of an undercut schottky metal lower layer (28, 44) into the active region of the semiconductor substrate. In one embodiment, the diffusion barrier (26) is provided at the base of the gold layer (30). In another embodiment, the gold layer (48) is encapsulated by the diffusion barrier (40) on the bottom (46) and sides (56). The diffusion barrier base layer is deposited. The diffusion barrier side layers are electroplated with the remaining portions of the contact structure being masked by selective oxidation.

T-type undercut electrical contact process on a semiconductor substrate

Method for fabrication of quasi-monolithic microwave integrated circuits in which metals, oxides, and processes are selected to enable fabrication of the circuits by first producing many layers of metals and oxides in situ without removing the circuit from its environmental chamber. This reduces inclusion of contaminating chemical films and particles between the desired layers. Circuit elements are then defined by processing of the layers by photolithography and other processes from the top of the circuit downward. Lumped and distributed capacitors, resistors, inductors, transmission lines, and contacts for active devices are monolithically defined, with a reduced number of process steps.

Method for fabricating quasi-monolithic integrated circuits

Making a buried channel FET with lateral growth over amorphous region

During fabrication of monolithic microwave integrated circuits, active devices having sources, gates, drains, and/or Schottky barrier junctions are first provided for an epitaxial layers. Then many layers of metals and oxides are produced thereover in situ without removing the circuit from its environmental chamber. Circuit elements are then defined by processing of the many layers sequentially by photolithography and other processes from the top of the chip downward. Certain combinations of metals, oxides, and processes are selected to enable fabrication of circuits from the top down in this way. This reduces inclusion of contaminating chemical films and particles between the desired layers. Lumped and distributed capacitors, resistors, inductors, transmission lines, contacts, and complete active devices are monolithically defined, with a reduced number of process steps. An all-refractory MESFET is described, having a Schottky barrier gate and nonalloyed ohmic contacts for source and drain producible at room temperatures. Source, gate, and drain can be defined with a single mask. A thinner gold layer is formed for FET contacts than for other circuit conductors and elements by means of a configured tantalum layer buried in a thick gold layer.

Method for fabrication of monolithic integrated circuits

The fabrication of high performance and reliable Buried Channel Field Effect Transistor (BCFET) using Schottky gate junction and heavily doped N layers for the source and drain electrode is described. The BCFET is composed of a semi-insulating substrate in which two N layers for the drain electrodes and one N layer for the source electrode are formed in one of the semi-insulating surface. The N source electrode is centrally located between the two N electrodes and all three lie in the same plane. The source and drain electrodes are separated by a thin semi-insulating layer, the length of which can range from 0.5 micron to several micron range, depending on the desired voltage breakdown. A Schottky gate is defined in an active N layer directly above the source N layer. The ohmic contacts for the source and drain N layers are defined several microns away from the Schottky junction, resulting in a considerable improvement in device reliability. Reliability is further enhanced by the fact that the resulting device is buried within the material where it is insulated from the ambient.

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Kings Park, NY, United States of America

Joseph A Calviello