Advanced Micro Devices Corporation

Joseph A Brcich

Om P Agrawal

Robert Alan Williams

Lance L Smith

David Gary Roberts

N Bruce Threewitt

Roy J Levy

Dervinn Deyual Caldwell

Jimmy R Madewell

Gerald G Isaac

Method and system for preventing electronic overstress during powering up a processor with voltage detection capabilities employing a mechanism for detecting the voltage requirements of the processor to be coupled into a motherboard and accordingly adjusts the power supply of the motherboard to the processor voltage requirements. The detection mechanism includes sensing of logic signals by sensing a voltage from one or more pins of the processor. Those pins are internally connected to ground or internally not connected thus facilitating sensing of logic signals prior to powering up the processor. The probed signals are used to control the power supplied to the processor by adjustment mechanisms applied to power regulator or programmable logic devices. Since the detection of the proper operating voltage requirements of the processor and the consequent adjustment of the voltage power to be supplied to the processor occur during the powering up of the processor, electrical over stress and potential damage of the processor are eliminated.

System and method for processor dual voltage detection and over stress protection

A reception indicator circuit is provided for use in an apparatus, wherein the apparatus enables a host system to receive information packets from a medium. The reception indicator circuit has a delay calculator, a byte count comparator and a signal asserter. The delay calculator selects and reads a reference delay value in one of N number of length-delay data storage elements. A reference length value contained in the one of N number of length-delay data storage elements corresponds to a length value of an information packet being received by the apparatus. The length value of the information packet is determined based on data in the information packet. The byte count comparator detects when the reference delay value number of bytes in the information packet have been received by the apparatus. The signal asserter asserts a reception indication signal when the byte count comparator detects that the reference delay value number of bytes in the information packet have been received by the apparatus. Alternatively, the reception indicator circuit may include a delay calculator that either calculates or selects an interrupt time. In such an alternate reception indicator circuit, the byte count comparator may be replaced by a delay comparator that determines when the interrupt time has elapsed. After the interrupt time has elapsed, the signal asserter asserts the reception indication signal. The apparatus may be a network peripheral, and the medium may be a communications network.

Information packet reception indicator for reducing the utilization of a host system processor unit

The present invention provides an output logic macrocell for controlling configuration of an output for an integrated circuit wich provides a logic signal including a register responsive to a clock signal for latching the logic signal to provide a registered signal. An output selector receives both the logic signal and the registered signal and selects responsive to an output select signal, either the logic signal or the registered signal. A feedback path provides a feedback signal as data which is selected by a feedback selector responsive to a feedback select signal for selecting the logic signal or the registered signal as the feedback signal. Further, a clock signal enable circuit, responsive to a clock enable signal, enables or disables the clock signal to clock the register. Accordingly, the register, the output selector, the feedback path, and the clock enable circuit are all dynamically controllable by respective control signals.

Programmable logic array using internally generated dynamic logic

A computer system having a central processing unit, a dynamic memory controller, an error detection and correction network and a dynamic memory for storing data that are subject to being refreshed and to data bit errors. The dynamic memory controller has a refresh mode for controlling access to the memory only to refresh the data, a refresh with error detection and correction mode, for controlling access to the memory to merge or simultaneous refresh a row of data while detecting and correcting data bit errors, and a read/write mode for controlling access to the memory in response to CPU requests for a read/write memory operation.

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San Jose, CA, United States of America

Joseph A Brcich