Intel Corporation

Joseph A Bennett

David I Poisner

Andrew H Gafken

Darren L Abramson

David Sastry

Jasmin Ajanovic

Prashant Sethi

Kenneth C Creta

Jose Andy Vargas

Randolph L Campbell

Mark Sullivan

Solomon B Trainin

Blaise B Fanning

Mikal Hunsaker

Randy B Osborne

Knut Stener Grimsrud

Zohar Bogin

Guoqing C Li

Sang-Hee Lee

Jeffrey R Wilcox

Michael N Derr

Charles E Narad

Karthi R Vadivelu

Dmitrii A Loukianov

George R Hayek

Anoop Mukker

Raul N Gutierrez

Gideon Prat

Pat Brouillette

Adit D Tarmaster

Vallabhajosyula Zulu Somayazulu

James Bury

Jim Bury

In one embodiment an electronic device includes a processor and at least one universal serial bus (USB) subsystem comprising logic, at least partially including hardware logic, configured to detect a connection from a remote electronic device to a USB port of the electronic device, determine whether the USB port of the electronic device is to act as an upstream facing port or a downstream facing port, and in response to a determination that the USB port of the electronic device is to be configured as an upstream facing port, to implement a port mapping process to map the USB port to one of a device controller or a debug controller. Other embodiments may be described.

System and method for universal serial bus (USB) protocol debugging

An approach is provided for determining a program clock reference (PCR) value validity, for avoiding inaccurate variable delay reference (VDR) values, and for avoiding a mismatch in a data packet between a sequence number and a packet number for a wireless display extension. The approach involves determining to generate a data packet carrier having an optional PCR value, a VDR) value, and a validity indicator. The approach may further involve processing the data packet carrier to determine whether the data packet carrier has the optional PCR value. The approach may also involve causing, at least in part, a surrogate PCR value to be generated based, at least in part, on a determined absence of the optional PCR value from the data packet carrier.

Method and apparatus for low jitter clock recovery in wireless display extensions

Machine-readable media, methods, and apparatus are described to issue message signaled interrupts. In some disclosed embodiments, a device generates message signaled interrupts in a manner that enables a device driver written with level-sensitive semantics to properly service the device despite the edge-triggered characteristics message signaled interrupts.

Apparatuses to provide a message signaled interrupt to generate a PCI express interrupt

Described within is a power management system for a computing platform that provides additional reductions in power consumption from that provided by only periodically putting the CPU or peripheral devices in low power non-operational states. In particular, the embodiment prevents the OS from generating an interrupt due to timer ticks while in a non-C0 state, until such time as a number of timer ticks have been gathered.

Method and apparatus of collecting timer ticks

Embodiments are generally direct to a method and apparatus to generate a data descriptor. In one embodiment, a data descriptor is generated for a block of data to be forwarded from a node to another node on a communication link. The data descriptor includes an indication to build a data packet containing at least a portion of the block of data in an accelerated or a non-accelerated manner.

Method and apparatus to generate a data descriptor

Driver transparent message signaled interrupts

In one embodiment, an apparatus to synchronize multiple controllers is disclosed. The apparatus comprises a plurality of controllers, and logic coupled to the plurality of controllers to control one or more controllers of the plurality of controllers to perform fetches simultaneously with one or more other controllers of the plurality of controllers. Other embodiments are also described.

Mechanism for synchronizing controllers for enhanced platform power management

Embodiments are generally direct to a method and apparatus for generating a header in a communication network. In one embodiment, receiving at a node on a first communication link a protocol data unit (PDU), generating a header that is non-specific to a particular communication protocol associated with the PDU when received at the node, the header to facilitate encapsulation and transportation of the PDU through a second communication link to deliver the PDU to a memory-based service interface of another node on the second communication link.

Method and apparatus for generating a header in a communication network

A method and apparatus are provided for operating a hot plug system. A first device may determine whether the system is to operate in one of a parallel mode or a serial mode. A second device may control a mode of the chipset based on the determination of the first device. The second device may include logic, a first multiplexer, a second multiplexer, a first converter and a second converter all provided on the chipset.

Apparatus and method for converting parallel and serial PCI hot plug signals

Methods and apparatuses to provide message signaled interrupts to level-sensitive drivers

A system includes a host that may be used to interface with an advanced technology attachment (ATA) device. The host includes at least one timer used to determine when to place the ATA device in a low power mode independently of an operating system (OS).

Method and apparatus of self-powering down ATA devices

Methods and systems for keeping two independent busses coherent that includes writing data from an Input/Output (I/O) controller to a memory. The I/O controller sends the data to the memory via a first bus connected between a first port of a memory controller and the I/O controller. A tag is sent from the I/O controller, after the data, via the first bus through the first port. The tag is received by the memory controller. Completion status of the data write is requested from the I/O controller by a processing unit. The request is sent to the I/O controller via a second bus connected between a second port of the memory controller and the I/O controller. The I/O controller waits for a tag acknowledgment from the memory controller before providing notification to the processing unit that the data write has completed. Therefore, the first bus and the second bus are coherent.

Method and system for keeping two independent busses coherent

An apparatus communicates with an advanced switching (AS) fabric. The apparatus includes a transmit engine that generates a request packet for transmission to the AS fabric. The transmit engine associates a first transaction identifier with the request packet. A receive engine receives a reply packet in response to the request packet. The reply packet contains a second transaction identifier. The receive engine compares the first transaction identifier to the second transaction identifier. If the first transaction identifier matches the second transaction identifier, the receive engine decides to store data from the reply packet at an address associated with the first transaction identifier.

Processing replies to request packets in an advanced switching context

One embodiment involves having a processor writing disk drive command information for a number of data transactions to cacheable system memory. The processor then performs a single write transaction to a disk drive host controller. The disk drive host controller then causes a DMA transfer to occur which reads the command information located in system memory and stores the command information in a queue. Once the host controller has the command information, it programs the disk drive with information corresponding to a queue entry over a serial interconnect. The disk drive signals an interrupt after it processes the command information. The disk drive host controller does not forward the interrupt to the processor, but services the interrupt itself. The disk drive host controller reads from the disk drive to determine the disk drive status. The disk drive can signal that it is ready to execute the programmed command, or it can signal that it is not ready to perform the programmed command but is ready to receive additional command programming information corresponding to another queue entry, or it may signal that it is ready to execute a previously programmed command. The disk drive host controller then performs the required operations using the information stored in the queue without involving the processor. Because the processor is only involved in setting up a command block in system memory and in signaling the disk drive host controller that the command block is ready for reading, the processor is freed up to perform other tasks and overall system performance is improved.

Hardware assisted ATA command queuing

Apparatus and method for parallel and serial PCI hot plug signals

Growing community of inventors

Roseville, CA, United States of America

Joseph A Bennett