Siemens Aktiengesellschaft

Infineon Technologies Ag

Josef Winnerl

Franz Neppl

Werner Reczek

Dezso Takacs

Erwin P Jacobs

Wolfgang Pribyl

Johann Alsmeier

Georg Tempel

Thomas Zettler

Georg Georgakos

Wolfgang Pockrandt

Xaver Guggenmos

Guenther Roeska

Carlos-Alberto Mazure-Espejo

Walter Neumueller

Walter Neumuller

A method for switching high positive or negative voltages to an output terminal of a circuit configuration includes connecting a series circuit of a first p-channel transistor and a first n-channel transistor between terminals for the two voltages. Gates of the two transistors are connected through load paths of transistors of the other respective conduction type to first and third input terminals. Gates of the transistors of the other conduction type are respectively connected to second and fourth input terminals. The first p-channel transistor and the first n-channel transistor can each be locked through load paths of transistors of the same conduction type which are connected between their gate terminals and the respective terminals for the high positive and high negative potential, and the gates of the transistors of the same conduction type are connected to the output terminal. Either the high positive potential or the high negative potential can be switched through to the output terminal depending on the potential at the input terminals.

Method for switching voltages higher than a supply voltage on a

A method for producing a via hole to a doped region in a semiconductor device, including the steps of: producing the doped region in a substrate such that the doped region is limited by insulating regions at least at a surface of the substrate; depositing an undoped silicon layer surface-wide on the substrate; producing a doped region in the silicon layer that overlaps a region for the via hole; selectively removing the undoped silicon of the silicon layer relative to the doped region of the silicon layer; producing an insulating layer surface-wide; and forming the via hole in the insulating layer by selective anisotropic etching relative to the doped region of the silicon layer.

Method for producing a via hole to a doped region

Solid-state memory device

Electrically erasable and programmable non-volatile storage location

Contact structure for vertical chip connections

Method for producing a semiconductor component with electrical

Bipolar transistor in a protective element for integrated circuits. A bipolar transistor is used as a part of a protective element against electrical high voltages for integrated circuits in their integrated and dismantled condition, this bipolar transistor being insulated from the integrated circuit. A base terminal of the bipolar transistor is connected to a first voltage reference, a collector terminal is connected to a second voltage reference and an emitter terminal is connected to an input or output of the integrated circuit that is to be protected. As a result of the interconnection of the bipolar transistor and as a result of the insulation of the semiconductor substrate, substrate currents that occur during operation are kept as low as possible and the danger of a 'latch-up' is thereby suppressed. The protective element may further contain an MOS field effect transistor or a resistive element.

Bipolar transistor as protective element for integrated circuits

Integrated circuit having anti latch-up circuit in complementary MOS circuit technology. Due to the incorporation of non-linear elements between the ground (V.sub.ss) and the p-conductive semiconductor substrate (P.sub.sub) and between the supply voltage (V.sub.DD) and the n-conductive semiconductor zone (N.sub.w), the risk of the occurrence of the latch-up effect triggered by the build-up of base charges at the parasitic vertical and lateral bipolar transistors is diminished. The space requirement for the non-linear elements to be additionally incorporated is low and the circuit properties of the MOS transistors are not influenced as a result thereof. The realization of the non-linear elements can ensue with Schottky contacts or with additional MOS transistors that are wired as diode elements. A realization in the form of buried diodes of polycrystalline silicon (PSi) is also possible, realized, for example, as barrier layer diodes.

Integrated circuit with anti latch-up circuit in complementary MOS

An integrated circuit containing bipolar and complementary MOS transistors wherein the base and emitter terminals of the bipolar transistor, as well as the gate electrodes of the MOS transistors, are composed of a silicide or of a double layer polysilicon silicide. The base and emitter terminals, as well as the gate electrodes, are arranged in one level of the circuit and there p.sup.+ doping or, respectively, n.sup.+ doping proceeds by ion implantation in the manufacture of the source/drain zones of the MOS transistors. As a result of the alignment independent spacing between the emitter and the base contact, the base series resistance is kept low and a reduction of the space requirement is achieved. Smaller emitter widths are possible by employing the polycide or silicide as diffusion source and as the terminal for the emitter. The size of the bipolar transistor is not limited by the metallization grid, since the silicide terminals can be contacted via the field oxide. The integrated semiconductor circuit is employed in VLSI circuits having high switching speeds.

Integrated circuit containing bi-polar and complementary MOS transistors

An integrated circuit in complementary circuit technology comprises a substrate bias voltage generator which reverse biases the substrate, into which tubs of opposite conductivity are inserted. The source regions of the field effect transistors arranged in the substrate lie at ground potential. In order to avoid 'latch-up' effects, the output of the substrate bias voltage generator is connected by way of an electronic switch to a circuit point lying at ground potential, whereby the switch is driven via the output of the substrate bias voltage generator.

Integrated circuit in complementary circuit technology comprising a

A circuit which contains integrated bipolar and complementary MOS transistors, including wells in the substrate for forming the MOS transistors, the wells also containing isolated bipolar transistors, the wells forming the collector of the bipolar transistor and being surrounded by trenches which are filled with doped polycrystalline silicon. The doped trench reduces the lateral out diffusion from the wells and thus serves to increase the packing density while serving as a collector contact region. The invention is employed in the manufacture of integrated semiconductor circuits having high switching speeds.

Circuit containing integrated bipolar and complementary MOS transistors

In an integrated circuit containing MOS transistors and/or bipolar transistors, the load resistors, which are arranged as thin-film elements on the field oxide zones which separate the active transistor zones, consist of polycrystalline silicon which is formed simultaneously with gate electrodes and/or the emitter and base terminal zones of the bipolar transistors on a substrate which contains the integrated circuit. The structuring of the load resistors is carried by way of an oxide mask which serves as an etch stop during the structuring of the gate electrode composed of a double layer of polysilicon and a silicide of a refractory metal. As only the polysilicon of the gate layer without overlying silicide is used for the load resistors, the sheet resistance of the load resistors can be set independently of that of the gates.

Method of making an integrated circuit comprising load resistors

For self-aligned manufacture of contacts referred to as vias between interconnects that are contained in wiring levels arranged above one another in an integrated circuit, a pillar technique is employed where the contacts are produced before the deposition of an inter-metal dielectric to produce the pillar, a layer structure is produced that contains at least one metal layer for the lower wiring level and at least one conductive layer for the contacts. The longitudinal expanse of the contact is defined by a mask that reliably overlaps the desired width of the lower interconnect. The transversal expanse of the contact is defined by the mask needed for producing the lower interconnect. The contacts and the lower interconnects are produced by step-by-step etching.

Method for self-aligned manufacture of contacts between interconnects

An integrated circuit executed in complementary circuit technology, has a substrate bias generator (16) which connects the substrate (1) to a substrate bias. A well (2) of opposite conductivity is inserted into the substrate (1), and FETs with complementary channels are inserted into the substrate (1) and into the well (2), respectively. The source regions (3) of the FET's of first conductivity lie at ground potential. In order to avoid latch-up effects, the output (17) of the substrate bias generator (16) is connected via an electronic switch (S1) to a circuit point (8) lying at ground potential, the switch being driven via a time-delay circuit (24) charged with the supply voltage so that it opens with a prescribed time-delay after the supply voltage is applied.

Growing community of inventors

Munich, Germany

Josef Winnerl