Infineon Technologies Ag

Siemens Aktiengesellschaft

Qimonda Ag

Infineon Technologies Flash Gmbh & Co. Kg

Qimonda Flash Gmbh

Other

Micronas Gmbh

Infineon Ag

Ingentix Gmbh & Co. Kg

Josef Willer

Franz Hofmann

Hans Reisinger

Wolfgang Krautschneider

Till Schl&ouml;sser

Christoph Ludwig

Hermann Wendt

Thomas Mikolajick

Volker Lehmann

Reinhard J Stengl

Paul-Werner Von Basse

Herbert Palm

Bernhard Sell

Emmerich Bertagnolli

Nicolas Nagel

Michael Specht

Corvin Liaw

Joachim Deppe

Christoph Kleint

Detlev Richter

Klaus-Dieter Ufert

Armin Kohlhase

Dirk Schumann

Doris Keitel-Schulz

Christoph Friederich

Barbara Hasler

Frank Lau

Ronald Kakoschke

Martin Franosch

Martin Gutsche

Thomas Scheiter

Bernd Goebel

Wolfgang Hoenlein

Veronika Polei

Norbert Schulze

Ulrike Gruning

Karl-Heinz Kuesters

Till Schloesser

Helmut Horst Tews

Georg Braun

Harald Seidl

Thomas Roehr

Roman Knoefler

Stephan Marksteiner

Christofer Hierold

Achim Gratz

Cay-Uwe Pinnow

Ralf Symanczyk

Thomas Peter Haneder

Dominik Olligs

Girolamo Gallo

Michael Bollu

Mayk Roehrich

Andreas Kux

Lars Bach

Frank Puschner

Jakob Kriz

Thomas Melde

Hans-Peter Zwicknagl

Herbert Sch&auml;fer

Andreas Spitzer

Jurgen Fischer

Guy LeFranc

Gert Koebernik

Torsten Mueller

Ulrike Gr&uuml;ning

Paul Werner Von Basse

Ramirez Xavier Veredas

Roberto Ravasio

Bernd Gobel

Juerg Haufe

Karl Heinz Kuesters

Thomas Pausch

Patrick Haibach

Paul-Werner Basse

Thomas Bohm

Karl-Heinz Tietgen

Franz Hoffmann

Dezs&ouml; Takacs

Annalisa Cappelani

Karl-Heinz Küsters

Roland Kakoschke

An integrated circuit is described. The integrated circuit may comprise a multitude of floating-gate electrodes, wherein at least one of the floating-gate electrodes has a lower width and an upper width, the lower width being larger than the upper width, and wherein the at least one of the floating-gate electrodes comprises a transition metal. A corresponding manufacturing method for an integrated circuit is also described.

Integrated circuit with floating-gate electrodes including a transition metal and corresponding manufacturing method

In an embodiment, a method for transferring data in a memory device is provided. The method may include transferring data from a first memory cell arrangement including a plurality of memory cells to a second memory cell arrangement including a plurality of memory cells via a connecting circuit arrangement coupled to the plurality of memory cell arrangements and providing a plurality of controllable connections via a plurality of connecting circuit terminals, the memory cell arrangements being connected with at least one connecting circuit terminal of the plurality of connecting circuit terminals, wherein the connecting circuit is configured to provide arbitrarily controllable signal flow connections between the plurality of connecting circuit terminals. The data are transferred via a logic connection using the controllable connections. Simultaneously, a further logic connection may be provided to a memory cell arrangement of the memory cell arrangements using the controllable connections.

Memory device and method providing logic connections for data transfer

An integrated circuit including a first gate stack and a second gate stack and a method of manufacturing is disclosed. One embodiment provides non-volatile memory cells including a first gate stack and a gate dielectric on a first surface section of a main surface of a semiconductor substrate, and a second gate stack including a memory layer stack on a second surface section. A first pattern is transferred into the first gate stack and a second pattern into the second gate stack.

Integrated circuit including a first gate stack and a second gate stack and a method of manufacturing

An integrated circuit is described. The integrated circuit may have: an active area line formed of a material of a semiconductor substrate with a first longitudinal direction parallel to an upper surface of the semiconductor substrate; wherein the active area line has at least one form-supporting element extending in a second longitudinal direction parallel to the upper surface of the semiconductor substrate; and wherein the second longitudinal direction is arranged with regard to the first longitudinal direction in an angle unequal to 0 degree and unequal to 180 degree.

Integrated circuit with an active area line having at least one form-supporting element and corresponding method of making an integrated circuit

A memory cell arrangement includes a first memory cell string having a plurality of serially source-to-drain-coupled transistors, at least some of them being memory cells, a second memory cell string having a plurality of serially source-to-drain-coupled transistors, at least some of them being memory cells. A dielectric material is between and above the first memory cell string and the second memory cell string. A source/drain line groove is defined in the dielectric material. The source/drain line groove extends from a source/drain region of one transistor of the first memory cell string to a source/drain region of the second memory cell string. Electrically conductive filling material is disposed in the source/drain line groove. Dielectric filling material is disposed in the source/drain line groove between the source/drain regions.

Memory cell arrangements

An integrated circuit having a memory cell arrangement with a plurality of memory cells and a memory cell arrangement controller is provided. The memory cell arrangement controller is configured such that during programming of at least one memory cell of the plurality of memory cells, at least one memory cell, which is arranged adjacent to the memory cell to be programmed, is driven to shield the memory cell to be programmed.

Integrated circuit, method to program a memory cell array of an integrated circuit, and memory module

A method of manufacturing at least one NAND-coupled semiconductor component is disclosed. A layer structure is formed on or above a semiconductor substrate. The layer structure is patterned to expose at least one region to be doped. The exposed region is doped and annealed. The patterned layer structure is at least partially removed. Replacing material is formed in the region in which the patterned layer structure has been removed, thereby forming the at least one NAND-coupled semiconductor component.

Method of manufacturing at least one semiconductor component and memory cells

A method for forming trenches on a surface of a semiconductor substrate is described. The method may include: etching a first plurality of trenches into the surface of the semiconductor substrate; filling the first plurality of trenches with at least one material; and etching a second plurality of trenches into every second trench of the first plurality of trenches. Furthermore, a method for forming floating-gate electrodes on a semiconductor substrate and an integrated circuit is described.

Method for forming trenches on a surface of a semiconductor substrate

Embodiments of the present invention relate generally to integrated circuits and methods for manufacturing an integrated circuit. In an embodiment of the invention, an integrated circuit having a memory cell is provided. The memory cell may include a trench in a carrier, a charge trapping layer structure in the trench, the charge trapping layer structure comprising at least two separate charge trapping regions, electrically conductive material at least partially filled in the trench, and source/drain regions next to the trench.

Integrated circuit having NAND memory cell strings

In an embodiment of the invention, an integrated circuit having a cell is provided. The cell may include a field effect transistor structure which includes a gate stack and a resistivity changing material structure disposed above the gate stack, wherein the resistivity changing material structure includes a resistivity changing material which is configured to change its resistivity in response to the application of an electrical voltage to the resistivity changing material structure.

Integrated circuit having a cell with a resistivity changing layer

Gate stacks of an array of memory cells and a plurality of select transistors are formed above a carrier, the gate stacks being separated by spacers. An opening is formed between the spacers in an area that is provided for a source line. A sacrificial layer is applied to fill the opening and is subsequently patterned. Interspaces are filled with a planarizing layer of dielectric material. The residues of the sacrificial layer are removed and an electrically conductive material is applied to form a source line.

Method of forming a semiconductor memory device and semiconductor memory device

An integrated circuit including a memory cell and a method of manufacturing the integrated circuit are described. The memory cell includes a buried gate select transistor and a resistive memory element coupled to the buried gate select transistor. The resistive memory element stores information based on a resistivity of the resistive memory element.

Resistive memory element and method of fabrication

A semiconductor memory having charge trapping memory cells and fabrication method thereof. The direction of current flow of each channel region of the memory transistors runs transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive local interconnects of source-drain regions are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and connected to the bit lines, wherein gate electrodes are arranged in trenches at least partly formed in the memory substrate.

Semiconductor memory having charge trapping memory cells and fabrication method thereof

In an embodiment of the invention, a method of operating an integrated circuit for reading the logical state of a selected one of a plurality of memory cells included within a memory cell string in the integrated circuit is provided.

Method of operating an integrated circuit for reading the logical state of a memory cell

The present invention relates generally to integrated circuits, to methods for manufacturing integrated circuits, and to integrated memory arrays.

Integrated circuits, methods for manufacturing integrated circuits, integrated memory arrays

Growing community of inventors

Riemerling, Germany

Josef Willer