International Business Machines Corporation

Globalfoundries Inc.

Josef S Watts

Hui Zang

Shesh Mani Pandey

Henry W Trombley

Duane E Galbi

William R Tonti

Wayne Frederick Ellis

Jagar Singh

Wagdi William Abadeer

Jerome Ciavatti

Badih El-Kareh

Tamilmani Ethirajan

Nathan R Hiltebeitel

Kent E Morrett

Calvin John Bittner

Satyasuresh V Choppalli

Rainer Thoma

Shrinivas J Pandharpure

Vaidyanathan T Subramanian

Prabhu R Dattatreya

Sourabh Khandelwal

Amit A Dikshit

Ruilong Xie

Edward J Nowak

Jack Allan Mandelman

Kerry Bernstein

Joseph Andrew Iadanza

Richard Quimby Williams

James Stuart Dunn

James Johnson

Ning Lu

Yi Qi

Oliver Kiehl

Stephen Arthur St Onge

Maria Gabrani

Eric Adler

Steven Alfred Grundon

Paul A Hyde

Jae Gon Lee

Jenifer E Lary

Scott Keith Springer

William H Guthrie

Ramya Viswanathan

Amr Y Abdo

James M Oberschmidt

Steven G Lovejoy

Yoo-Mi Lee

Nathalie Casati

Robinson E Pino

James P Hoffmann

John R Jones

One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a gate stack having a gate conductor therein over a substrate, the gate stack being within a dielectric layer; a source/drain contact to a source/drain region over the substrate and adjacent to the gate stack within the dielectric layer; an upper conductor extending above, without contacting, the source/drain contact, wherein the upper conductor extends within the dielectric layer to contact the gate conductor within the gate stack.

Integrated circuit structure having gate contact and method of forming same

Semiconductor structures and methods of forming semiconductor structures. Trench isolation regions arranged to surround an active device region The trench isolation regions extend through a device layer and a buried oxide layer of a silicon-on-insulator wafer into a substrate of the silicon-on-insulator wafer. A well is arranged in the substrate outside of the trench isolation regions, and a doped region is arranged in a portion of the substrate. The doped region is arranged in a portion of the substrate that is located in a horizontal direction adjacent to one of the trench isolation regions and in a vertical direction adjacent to the buried oxide layer. The doped region and the well have the same conductivity type.

SOI device structures with doped regions providing charge sinking

A resistor body is separated from a doped well in a substrate by a resistor dielectric material layer. The doped well is defined by at least one doped region and can include a dopant gradient in the doped well to reduce parasitic capacitance of the resistor structure while retaining heat dissipation properties of the substrate. The resistor body is formed in a cavity in a dielectric layer deposited on the substrate, which deposition can be part of a concurrent fabrication, such as part of forming shallow trench isolations, and the cavity can be lined with the resistor dielectric material.

Semiconductor device resistor structure

A semiconductor structure includes a substrate and a vertical FinFET disposed over the substrate. The vertical FinFET includes: The 1and 2metal gates are electrically isolated from each other by the fin.

Double gate vertical FinFET semiconductor structure

A method includes providing a semiconductor structure having a substrate and a plurality of fins extending upwards from the substrate. A CT pillar layer is disposed over the semiconductor structure. A CT mask is lithographically patterned over the CT pillar layer. The CT mask is anisotropically etched to remove exposed portions of the CT pillar layer and to form a CT pillar between the fins. A dummy gate structure is disposed across the CT pillar. The dummy gate structure is replaced with first and second metal gate structures that are electrically isolated from each other by the CT pillar.

Methods of forming a CT pillar between gate structures in a semiconductor

A method of forming an integrated circuit includes forming a FinFET by: forming a semiconductor fin on a semiconductor substrate; forming a first source/drain region in the semiconductor substrate under a first end of the semiconductor fin and a second source/drain region in the semiconductor substrate under a second, opposing end of the semiconductor fin, the second source/drain region separated from the first source/drain region by a portion of the semiconductor substrate having an opposite doping from that of the first and second source/drain region; and forming a surrounding gate extending about the semiconductor fin above the semiconductor substrate. A second vertical FinFET may be formed simultaneously. The method allows the FinFET to have a long channel extending laterally through its fin compared to the short channel of the vertical FinFET, thus creating short channel and long channel devices together without impacting vertical FinFET height.

Forming long channel FinFET with short channel vertical FinFET and related integrated circuit

A vertical FinFET structure includes a metal layer disposed between adjacent fins of a multi-fin device. The metal layer, which is in electrical contact with a self-aligned work function metal layer, is adapted to decrease the overall resistance of the gate contact for the device. A lower gate contact resistance can improve the reliability and performance of the device, particularly in radio frequency (RF) applications. The metal layer can also extend laterally to provide a contact region for a gate contact.

Vertical fin gate structure for RF device

One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a gate stack having a gate conductor therein over a substrate, the gate stack being within a dielectric layer; a source/drain contact to a source/drain region over the substrate and adjacent to the gate stack within the dielectric layer; a conductor extending above, without contacting, the source/drain contact and extending within the dielectric layer to contact the gate conductor within the gate stack.

Various embodiments include approaches for predicting unity gain frequency in a MOSFET. In some cases, a method includes predicting a unity gain frequency (f) in a MOSFET device in a manufacturing line, the method including: measuring a first set of in-line direct current (DC) parameters of the MOSFET on the manufacturing line at a first drain voltage (V); extracting a transconductance (G) from the first set of in-line DC parameters as a function of a gate-voltage (V) and the first drain-voltage (V); measuring a second set of in-line DC parameters of the MOSFET on the manufacturing line at a second drain voltage (V); extracting a total gate capacitance (C) from the second set of in-line DC parameters as a function of the gate-voltage (V); and predicting the unity gain frequency (f) of the MOSFET based upon the extracted transconductance (G) and the extracted total gate capacitance (C).

Methods of predicting unity gain frequency with direct current and/or low frequency parameters

The disclosure provides a vertical FinFET structure, including: a substrate including a first source/drain region; a looped channel region positioned on the first source/drain region of the substrate, the looped channel region having an inner perimeter which surrounds a hollow interior of the looped channel region; a first gate positioned within the hollow interior of the looped channel region, wherein the first gate is formed onto the looped channel region along the inner perimeter of the looped channel region; and a second source/drain region positioned on and overlying an upper surface of the looped channel region.

Vertical transistor structure with looped channel

One illustrative DRAM structure disclosed herein includes a first memory cell pair, a second memory cell pair, a single diffusion break (SDB) isolation structure positioned between the first and second memory cell pairs, and a single first gate positioned between the first and second memory cell pairs and above the SDB isolation structure.

DRAM structure with a single diffusion break

Methods of forming a self-aligned CT pillar with the same CD width as the device fins to enable PC isolation and the resulting devices are provided. Embodiments include forming a plurality of fins over a substrate; forming an oxide layer over the substrate and between each fin; removing a portion of a central fin among the plurality, a trench formed in the oxide layer; forming a CT pillar in the trench; recessing the oxide layer below an upper surface of the plurality of fins; forming a gate over the plurality of fins and CT pillar; planarizing the gate down to the CT pillar; and forming a cap layer over the gate and CT pillar.

Ultra-scale gate cut pillar with overlay immunity and method for producing the same

Diodes for use in FinFET technologies having increased junction electric fields without the need for increased dopant concentrations, as well as methods, apparatus, and systems for fabricating such diodes. The diodes may comprise a semiconductor substrate and a plurality of fins formed on the semiconductor substrate; wherein each of the plurality of fins comprises an N channel doped region comprising an N channel dopant, and the semiconductor substrate further comprises a plurality of P channel doped regions comprising a P channel dopant, wherein each of the P channel doped regions is disposed under one of the plurality of fins and is adjacent to the N channel doped region of the fin.

Method, apparatus, and system for increasing junction electric field of high current diode

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South Burlington, VT, United States of America

Josef S Watts