Infineon Technologies Ag

Josef Maerz

Petteri Palm

Chee Yang Ng

Chee Voon Tan

Ralf Otremba

Thorsten Meyer

Josef Hoeglauer

Oliver Haeberlen

Martin Gruber

Thorsten Scharf

Chau Fatt Chiang

Swee Kah Lee

Frank Daeche

Thomas Stoek

Manfred Kotek

Liu Chen

Michael Juerss

Joost Larik

Martin Benisek

Bun Kian Tay

Nikolaus Bott

Mark Pavier

Wae Chet Yong

Stefan Macheiner

Theng Chao Long

Sergey Yuferev

Stuart Cardwell

Nurfarena Othman

Clive O'Dell

Hock Siang Chua

Paul Armand Asentista Calo

Joseph Victor Soosai Prakasam

Hong Hock Tay

Mei Yih Goh

A package and method of manufacturing a package is disclosed. In one example, a package which comprises a first transistor chip having a first source pad and a second transistor chip having a second source pad and being stacked with the first transistor chip at an interface area. The first source pad and the second source pad are coupled at the interface area.

Stacked transistor chip package with source coupling

A power electronic assembly includes a board having metal layers laminated onto or between electrically insulating layers, and a laminate inlay embedded in the board. A first metal layer provides electrical contacts at a first side of the board. A second metal layer provides a thermal contact at a second side of the board. A third metal layer is positioned between the first metal layer and the laminate inlay and configured to distribute a load current switched by the laminate inlay. A fourth metal layer is positioned between the second metal layer and the laminate inlay and configured as a primary thermal conduction path for heat generated by the laminate inlay during switching of the load current. A first electrically insulating layer separates the fourth metal layer from the second metal layer so that the fourth metal layer is electrically isolated from but thermally connected to the second metal layer.

Power electronic assembly having a laminate inlay and method of producing the power electronic assembly

A power electronic assembly includes a board having metal layers laminated onto or between electrically insulating layers, and a power device embedded in the board. A first metal layer provides electrical contacts at a first side of the board. A second metal layer provides a thermal contact at a second side of the board. A third metal layer is positioned between the first metal layer and the power device and configured to distribute a load current switched by the power device. A fourth metal layer is positioned between the second metal layer and the power device and configured as a primary thermal conduction path for heat generated by the power device during switching of the load current. A first electrically insulating layer separates the fourth metal layer from the second metal layer so that the fourth metal layer is electrically isolated from but thermally connected to the second metal layer.

Power electronic assembly and method of producing thereof

A molded semiconductor package includes a lead frame having one or more first leads monolithically formed with a die pad and extending outward from the pad in a first direction. A semiconductor die is attached to the die pad at a first side of the die. A metal clip of a clip frame is attached to a power terminal at a second side of the die. One or more second leads monolithically formed with the metal clip extend outward from the clip in a second direction different than the first direction. A mold compound embeds the die. The first lead(s) and the second lead(s) are exposed at different sides of the mold compound and do not vertically overlap with one another. Within the mold compound, the clip transitions from a first level above the power terminal to a second level in a same plane as the leads.

Clip frame assembly, semiconductor package having a lead frame and a clip frame, and method of manufacture

A semiconductor device includes a conductive frame comprising a die attach surface that is substantially planar, a semiconductor die comprising a first load on a rear surface and a second terminal disposed on a main surface, a first conductive contact structure disposed on the die attach surface, and a second conductive contact structure on the main surface. The first conductive contact structure vertically extends past a plane of the main surface of the semiconductor die. The first conductive contact structure is electrically isolated from the main surface of the semiconductor die by an electrical isolation structure. An upper surface of the electrical isolation structure is below the main surface of the semiconductor die.

Semiconductor assembly with conductive frame for I/O standoff and thermal dissipation

A method of producing a molded semiconductor package includes: attaching a first load terminal at a first side of a semiconductor die to a leadframe, the semiconductor die having a second load terminal at a second side opposite the first side and a control terminal at the first side or the second side; encapsulating the semiconductor die in a laser-activatable mold compound so that the leadframe is at least partly exposed from the laser-activatable mold compound at a first side of the molded semiconductor package, and the second load terminal is at least partly exposed from the laser-activatable mold compound at a second side of the molded semiconductor package opposite the first side; and laser activating a first region of the laser-activatable mold compound to form a first laser-activated region that is electrically conductive.

Double-sided cooled molded semiconductor package

A method of producing a molded semiconductor package includes: attaching a first load terminal at a first side of a semiconductor die to a leadframe, the semiconductor die having a second load terminal at a second side opposite the first side and a control terminal at the first side or the second side; encapsulating the semiconductor die in a laser-activatable mold compound so that the leadframe is at least partly exposed from the laser-activatable mold compound at a first side of the molded semiconductor package, and the second load terminal is at least partly exposed from the laser-activatable mold compound at a second side of the molded semiconductor package opposite the first side; and laser activating a first region of the laser-activatable mold compound to form a first laser-activated region which forms part of an electrical connection to the second load terminal.

Molded semiconductor package with double-sided cooling

A semiconductor package includes a frame having an insulative body with a first main surface and a second main surface opposite the first main surface, a first plurality of metal traces at the first main surface, and a first cavity in the insulative body. A thermally and/or electrically conductive material filling the first cavity in the insulative body and having a different composition than the first plurality of metal traces. The thermally and/or electrically conductive material provides a thermally and/or electrically conductive path between the first and the second main surfaces of the insulative body. A semiconductor die attached to the frame at the first main surface of the insulative body is electrically connected to the first plurality of metal traces and to the thermally and/or electrically conductive material filling the first cavity in the insulative body. A corresponding method of manufacture is also described.

Semiconductor package having a filled conductive cavity

The invention relates to a vertical arrangement of at least two semiconductor components which are electrically insulated from one another by at least one passivation layer. The invention likewise relates to a method for fabricating such a semiconductor arrangement. A semiconductor arrangement is specified in which, inter alia, the risk of cracking at the metallization edges, for example, caused by thermomechanical loading, is reduced and the fabrication-dictated high content of radical hydrogen is minimized. Furthermore, a method for fabricating such a semiconductor arrangement is specified.

Semiconductor arrangement

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Oberhaching, Germany

Josef Maerz