Infineon Technologies Austria Ag

Infineon Technologies Ag

Josef Höglauer

Ralf Otremba

Klaus Schiess

Jürgen Schredl

Xaver Schlögel

Bernhard Knott

Joachim Mahler

Khalil Hosseini

Thorsten Scharf

Christoph Sandner

Uwe Jansen

Chooi Mei Chong

Fabio Brucchi

Johannes Lodermeyer

Manfred Schindler

Gerhard Nöbauer

Silke Auchter

Roman Riederer

Wolfgang Peinhopf

Stephan Auer

Clemens Rössler

Martin Pölzi

Günther Lohmann

A cryostat socket for holding an ion trap device mounted on a substrate in a cryostat includes a housing frame provided for pre-assembly in the cryostat. A pin insert is arranged in the housing frame. The pin insert includes a base plate and contact pins. The contact pins are arranged in an array. A housing cover has a receptacle for the substrate. The housing cover, when assembled with the housing frame, exerts a compressive force on a front side of the substrate by which a rear side of the substrate is pressed onto the contact pins.

Cryostat socket for holding an ion trap device mounted on a substrate in a cryostat

A connection structure is provided that includes a semiconductor substrate, a first layer arranged on the semiconductor substrate, the first layer being configured to provide shielding against radioactive rays, a second layer arranged on the first layer, the second layer including solder including Pb, and an electrically conductive member arranged on the second layer.

Connection structure and electronic component

A semiconductor package includes a semiconductor die and a metal clip. In one embodiment, the semiconductor die is embedded in an insulating material and has a first surface facing in a first direction, a second surface facing in a second direction opposite the first direction and an edge extending between the first and second surfaces. The metal clip is embedded in the insulating material above the die and bonded to the second surface of the die. Part of the metal clip extends laterally beyond the edge of the die and vertically in the first direction to provide galvanic redistribution at the second surface of the die. Other embodiments of semiconductor packages are also provided.

Chip-embedded packages with backside die connection

A power converter is described that includes components arranged within a first die and a second die of a single package. The first die includes one or more first switches coupled to a switching node of a power stage. The second die includes one or more second switches coupled to the switching node of the power stage, a feedback control unit configured to detect a current level at the one or more second switches of the power stage, and a controller unit configured to control the one or more first switches and the one or more second switches of the power stage based at least in part on the current level detected by the feedback control unit.

Switched-mode power converter with split partitioning

An electronic component includes at least one semiconductor device and a redistribution board comprising at least two nonconductive layers and a conductive redistribution structure. The semiconductor device is embedded in the redistribution board and electrically coupled to the redistribution structure and the redistribution board has a side face with a step. An outer contact pad of the redistribution structure is arranged on the step.

Electronic component, arrangement and method

A semiconductor packaging arrangement includes a transistor device including a first side including a source electrode and a gate electrode, a die pad having a first surface, and a lead having a first surface. A first conductive member is arranged between the source electrode and the first surface of the die pad and spaces the source electrode from the first surface of the die pad by a distance that is greater than a distance between the gate electrode and the first surface of the lead.

Semiconductor packaging arrangement

A semiconductor die includes a semiconductor body, a transistor device disposed in the semiconductor body and having a gate, a source and a drain, and a sense device disposed in the semiconductor body and operable to sense a parameter associated with the transistor device. The die further includes a source pad at a first side of the semiconductor body and electrically connected to the source of the transistor device, a drain pad at a second side of the semiconductor body opposing the first side and electrically connected to the drain of the transistor device, and a sense pad at the second side of the semiconductor body and spaced apart from the drain pad. The sense pad is electrically connected to the sense device. A corresponding package and method of manufacturing are also disclosed.

Semiconductor die and package with source down and sensing configuration

A semiconductor package includes a base, a die attached to the base, a lead and a connector electrically connecting the lead to the die. A mold compound encapsulates the die, the connector, at least part of the base, and part of the lead, so that the lead extends outward from the mold compound. An electrical insulation layer separate from the mold compound is attached to a surface of the mold compound over the connector. The electrical insulation layer has a fixed, defined thickness so that the package has a guaranteed minimum spacing between an apex of the connector and a surface of the electrical insulation layer facing away from the connector.

Semiconductor package with top-side insulation layer

A first electrode at a first side of a first semiconductor die is connected to a first conductive region of a substrate. A first electrode at a first side of a second semiconductor die is connected to a second conductive region of the substrate. Each die has a second electrode at an opposing second side of the respective die. A first metal layer extends from a periphery region of the substrate to over the first die. The first metal layer has a generally rectangular cross-sectional area and connects one of the conductive regions in the periphery region of the substrate to the second electrode of the first die. A second metal layer separate from the first metal layer extends over the first and second dies. The second metal layer has a generally rectangular cross-sectional area and connects the second electrodes of the first and second dies.

Multi-die package with separate inter-die interconnects

A semiconductor package includes a semiconductor die having a first electrode at a first side and a second electrode at a second side opposing the first side, a first lead under the semiconductor die and connected to the first electrode at a first level of the package, and a second lead having a height greater than the first lead and terminating at a second level in the package above the first level, the second level corresponding to a height of the semiconductor die. A connector of a single continuous planar construction over the semiconductor die and the second lead is connected to both the second electrode and the second lead at the same second level of the package.

Multi-level semiconductor package

A redistribution board includes a first conductive layer including a redistribution structure for low voltage signals, a second conductive layer including a redistribution structure for high voltage signals, and a non-conductive layer. The second conductive layer is spaced apart from the first conductive layer by the non-conductive layer. The redistribution board further includes a conductive connector extending from a mounting surface of the redistribution board to the second conductive layer. The conductive connector is surrounded by a low voltage trace of the first conductive layer.

Redistribution board, electronic component and module

A semiconductor device with a number of integrated coils is disclosed. In one embodiment, a first coil portion and a second coil portion are at least in part overlapping each other. Another embodiment provides a process for manufacturing a semiconductor device having at least the processes of generating a first coil portion, generating a second coil portion, wherein at least a part of the first coil portion and a part of the second coil portion are overlapping each other.

Semiconductor device with integrated coils

An integrated circuit includes a substrate and an inductive device on a first side of the substrate. The integrated circuit includes a first ferromagnetic material on a second side of the substrate opposite the first side.

Growing community of inventors

Heimstetten, Germany

Josef Höglauer