Emc Corporation

Josef Ezra

Adi Ofer

Yechiel Yochai

Eli Shagam

Orit Levin-Michael

Yedidia Atzmony

Daniel Lambright

Amnon Naamad

Sachin More

Ofer Michael

Lee W Sapiro

David Shadmon

Ohad Zeliger

Avihu Goral

Dar S Efroni

Described are techniques and criteria used in connection with cache management. The cache may be organized as a plurality of memory banks in which each memory bank includes a plurality of slots. Each memory bank has an associated control slot that includes groups of extents of tags. Each cache slot has a corresponding tag that includes a bit value indicating the availability of the associated cache slot, and a time stamp indicating the last time the data in the slot was used. The cache may be shared by multiple processors. Exclusive access of the cache slots is implemented using an atomic compare and swap instruction. The time stamp of slots in the cache may be adjusted to indicate ages of slots affecting the amount of time a particular portion of data remains in the cache. Each director may obtain a cache slot from a private stack of nondata cache slots in addition to accessing a shared cache used by all directors.

Private slot

Described are techniques for detecting incompatibilities. A first contents of a data item is determined in accordance with a first set of conventions associated with a first processor architecture. A second contents of said data item is determined in accordance with a second set of conventions associated with a second processor architecture and including at least one convention that is not included in said first set. An actual difference between the first contents and the second contents is determined. It is determined whether the actual difference is expected. If the actual difference is not expected, the data item is flagged as an incompatibility candidate. Code referencing the data item is examined to determine any coding incompatibilities due to coding dependencies.

Techniques for detecting coding incompatibilities

Described are techniques for determining a cache slot. A set of criteria for each of a plurality of families is received. A received data operation associated with a first of said plurality of families is obtained. It is determined, in accordance with the criteria associated with the received data operation, whether to allocate a cache slot in the cache for the received data operation. The criteria for the first family includes a minimum value and a maximum value used in determining a cache partition size range for the first family. The maximum value is used in determining a maximum cache partition size allowable for the first family.

Dynamic cache partitioning

In a method for testing computer code, each branch that occurs within the machine-readable code is located. A first tracepoint is placed immediately after the beginning of the branch and a second tracepoint at the target address of each branch, each tracepoint generating an indicator. When the machine-readable code with the tracepoints is executed on the target computer, the method identifies those indicators that have been generated by their corresponding tracepoints, thereby permitting determination of those branches that the program control flow has not passed through. The test cases are modified to exercise the previously omitted branches, and the converted code is re-executed, until all branches have been properly exercised. The tracepoints are automatically eliminated after they have performed their intended function.

Software debugging tool

A method for controlling exclusive access to a resource shared by multiple processors in a data storage system includes providing a system lock procedure to permit a processor to obtain a lock on the shared resource preventing other processors from accessing the shared resource and providing a faked lock procedure to indicate to the system lock procedure that a processor has a lock on the shared resource where such a lock does not exist, and wherein the faked lock procedure prevents another processor from obtaining the lock on the shared resource, but does not prevent other processors from accessing the shared resource. A data storage system according to the invention includes a shared resource, a plurality of processors coupled to the shared resource through a communication channel, and a lock services procedure providing the system lock procedure and the faked lock procedure. In one embodiment, the shared resource is a cache and the system lock procedure permits a processor to lock the entire cache whereas the faked lock procedure is implemented by a processor seeking exclusive access of a cache slot.

Method and apparatus for controlling exclusive access to a shared resource in a data storage system

A debugger mechanism that provides for debugging source code of a target by correlating messages in a log file associated with source code with corresponding lines of the source code.

Sequential event monitoring module

Described are techniques and criteria used in connection with cache management. The cache may be organized as a plurality of memory banks in which each memory bank includes a plurality of slots. Each memory bank has an associate control slot that includes groups of extents of tags. Each cache slot has a corresponding tag that includes a bit value indicating the availability of the associated cache slot, and a time stamp indicating the last time the data in the slot was used. The cache may be shared by multiple processors. Exclusive access of the cache slots is implemented using an atomic compare and swap instruction. The time stamp of slots in the cache may be adjusted to indicate ages of slots affecting the amount of time a particular portion of data remains in the cache.

Cache management via statistically adjusted time stamp queue

A method for estimating the fall through time of a cache includes maintaining local statistics associated with each data cache slot replaced by a processor, reading from a memory global statistics related to each data cache slot replaced by a plurality of processors, calculating new global statistics, and estimating a fall through time of the cache in response to the global statistics at a predetermined rate. When the global statistics are the result of at least a threshold number of data cache slots having been replaced, the new global statistics are calculated by weighting the global statistics by a factor of less than one and adding the weighted global statistics to the local statistics. When the global statistics are not the result of at least a threshold number of data cache slots having been replaced, the new global statistics are calculated by adding a time related to the lapsed time to a global sum value associated with the time stamp difference of the replaced data cache slots. In a multi-processor computer system, each of the processors accesses the global memory to update the global statistics at a different time. The fall through time is estimated continuously at a first predetermined rate and the global statistics are updated at a second predetermined rate that, in one embodiment, is a multiple of the first predetermined rate.

Cache fall through time estimation

Described are techniques used in connection with cache management. Data included in a cache slot is put 'on parole' with a first cache hit while waiting for subsequent cache hits. If a subsequent hit is received to the cache slot, it remains in the cache for a longer time period than a slot having only a first cache hit. The cache may be organized as a plurality of memory banks of cache slots. Each memory bank has an associated control slot that includes groups of extents of tags. Each cache slot has a corresponding tag, and a time stamp. The time stamp of slots in the cache may be adjusted affecting the amount of time a particular portion of data remains in the cache.

Method for cache management for positioning cache slot

A method and apparatus for cache management in a data storage system is presented. A table with tags corresponding to cache slots in a cache memory is provided. A copy of the table is stored in a local buffer in response to a request for allocation of one of the cache slots. The locally buffered table is used to make the requested cache slot allocation. A set of control parameters associated with the locally buffered table is used to determine if the locally buffered table can be re-used for cache slot allocation in response to a subsequent request for cache slot allocation. User-selectable levels are provided to control the degree of locally buffered table re-use. The user-selectable levels determine which values of the control parameters are used.

Locally buffered cache extensions having associated control parameters to determine use for cache allocation on subsequent requests

Described are various quality of service (QOS) parameters that may be used in characterizing device behavior in connection with a cache. A Partition parameter indicates which portions of available cache may used with data of an associated device. A Survival parameter indicates how long data of an associate device should remain in cache after use. A Linearity parameter indicates a likelihood factor that subsequent data tracks may be used such that this parameter may be used in determining whether to prefetch data. A Flush parameter indicates how long data should remain in cache after a write pending slot is returned to cache after being written out to the actual device. The QOS parameters may be included in configuration data. The QOS parameter values may be read and/or modified.

QOS feature knobs

A debugger mechanism to support multiple active targets and efficient switching between multiple active targets, in particular, heterogeneous targets, in a multiprocessing environment.

Debugging tool for efficient switching between targets in a multi-processor environment

The cache arrangement includes a cache that may be organized as a plurality of memory banks in which each memory bank includes a plurality of slots. Each memory bank has an associated control slot that includes groups of extents of tags. Each cache slot has a corresponding tag that includes a bit value indicating the availability of the associated cache slot, and a time stamp indicating the last time the data in the slot was used. The cache may be shared by multiple processors. Exclusive access of the cache slots is implemented using an atomic compare and swap instruction. The time stamp of slots in the cache may be adjusted to indicate ages of slots affecting the amount of time a particular portion of data remains in the cache. Associated with each processor is a unique extent increment used to determine a next location for that particular processor when attempting to locate an available slot.

Advancing bank pointer in prime numbers unit

The invention features a method and a system for selecting a slot within a memory unit, e.g., cache, for removal. The memory unit is accessible to a plurality of processors, and each slot in the memory unit has a corresponding entry in an age table. Each time when a processor examines one of the entries, an age value of the entry is increased. When the age value is above a maturity age, the corresponding slot becomes a removable slot. Each processor also maintains statistics to estimate the number of removable slots in the memory unit. According to the statistics, adjusts a maturity age associated with the processor dynamically and independently to control the number of removable slots. Accordingly, the number removable slots can be maintained at a pre-determined percentage relative to the total number of slots in the memory unit.

Growing community of inventors

Ashland, MA, United States of America

Josef Ezra