Infineon Technologies Ag

Josef Boeck

Maciej Wojnowski

Rudolf Lachner

Walter Hartner

Wolfgang Liebl

Ernst Seler

Herbert Schaefer

Thorsten Meyer

Herbert Knapp

Klaus Aufinger

Thomas Meister

Martin Franosch

Wolfgang Klein

Klaus Goller

Juergen Holz

Karl-Heinz Allers

Adrian Berthold

Markus Zeiler

A semiconductor package having an antenna; and a semiconductor die which is coupled to the antenna and comprises a transmitter configured to transmit wirelessly via the antenna a wireless signal having information on a local oscillator signal to a further semiconductor package comprising a further semiconductor die.

Transmission of wireless signal having information on a local oscillator signal

A method of manufacturing a semiconductor device package includes placing a semiconductor chip on a carrier, covering the semiconductor chip with an encapsulation material to form an encapsulation body, providing a microwave component having at least one electrically conducting wall structure integrated in the encapsulation body, and forming an electrical interconnect configured to electrically couple the semiconductor chip and the microwave component.

Method of manufacturing a semiconductor package having a semiconductor chip and a microwave component

A wireless communication system includes a first semiconductor module and a second semiconductor module. The first semiconductor module includes a semiconductor die connected to an antenna structure. The semiconductor die of the first semiconductor module and the antenna structure of the first semiconductor module are arranged within a common package. The semiconductor die of the first semiconductor module includes a transmitter module configured to transmit the wireless communication signal through the antenna structure of the first semiconductor module. The second semiconductor module includes a semiconductor die connected to an antenna structure. The semiconductor die of the second semiconductor module includes a receiver module configured to receive the wireless communication signal through the antenna structure of the second semiconductor module from the first semiconductor module.

Wireless communication system, a radar system and a method for determining a position information of an object

A bipolar transistor and a method for fabricating a bipolar transistor are disclosed. In one embodiment the bipolar transistor includes a semiconductor body including a collector region and a base region arranged on top of the collector region, the collector region being doped with dopants of a second doping type and the base region being at least partly doped with dopants of a first doping type and an insulating spacers arranged on top of the base region. The semiconductor body further includes a semiconductor layer including an emitter region arranged on the base region and laterally enclosed by the spacers, the emitter region being doped with dopants of the second doping type forming a pn-junction with the base region, wherein the emitter region is fully located above a horizontal plane through a bottom side of the spacers.

Bipolar transistor

A method of manufacturing an array of semiconductor device packages includes placing a plurality of semiconductor chips on a temporary carrier, covering the plurality of semiconductor chips with an encapsulation material to form an encapsulation body, providing a plurality of microwave components each including at least one electrically conducting wall structure integrated in the encapsulation body, forming a plurality of electrical interconnects each configured to electrically couple a semiconductor chip and a microwave component, and separating the encapsulation body into single semiconductor device packages each including a semiconductor chip, a microwave component and an electrical interconnect.

Method of manufacturing a semiconductor package having an integrated microwave component

A microwave device includes a semiconductor package comprising a microwave semiconductor chip and a waveguide part associated with the semiconductor package. The waveguide part is configured to transfer a microwave waveguide signal. It includes one or more pieces. The microwave device further includes a transformer element configured to transform a microwave signal from the microwave semiconductor chip into the microwave waveguide signal or to transform the microwave waveguide signal into a microwave signal for the microwave semiconductor chip.

Transition between a plastic waveguide and a semiconductor chip, where the semiconductor chip is embedded and encapsulated within a mold compound

A semiconductor device package includes an encapsulant and a semiconductor chip. The semiconductor chip is at least partly embedded in the encapsulant. A microwave component including at least one electrically conducting wall structure is integrated in the encapsulant. Further, the semiconductor device package includes an electrical interconnect configured to electrically couple the microwave component to the semiconductor chip.

Semiconductor package with integrated microwave component

A method includes providing a first semiconductor chip comprising a ring-shaped metal structure extending along a contour of a first main surface of the semiconductor chip. The method includes encapsulating the first semiconductor chip with an encapsulation body thereby defining a second main surface and depositing a metal layer over the first semiconductor chip and the encapsulation body. A plurality of external contact pads are placed over the second main surface of the encapsulation body, the metal layer electrically coupling at least one external contact pad of the plurality of external contact pads to the ring-shaped metal structure. A seal ring is placed between the ring-shaped metal structure and the contour of the first main surface of the first semiconductor chip.

Method of forming a ring-shaped metal structure

A semiconductor module having one or more integrated antennas in a single package is provided herein. The semiconductor module has a bonding interconnect structure that connects an integrated package to a printed circuit board (PCB), wherein the integrated antenna structures are located at greater center-to-center distance from the IC device than the three dimensional interconnect structures. Therefore, the bonding interconnect structures are confined to a connection area that causes a part of the package containing the one or more antenna structures to extend beyond the bonding interconnect structure as a cantilevered structure. Such a bonding interconnect structure result in a package that is in contact with a PCB at a relatively small area that supports the load of the package.

Integrated antennas in wafer level package

A method and a system for providing fusing after packaging of semiconductor devices are disclosed. In one embodiment, a semiconductor device is provided comprising a substrate comprising a fuse area, at least one fuse disposed in the fuse area, and at least one layer disposed over the substrate, wherein the at least one layer comprises at least one opening exposing the at least one fuse.

Method and system for providing fusing after packaging of semiconductor devices

A semiconductor module having one or more integrated antennas in a single package is provided herein to comprise a bonding interconnect structure having a plurality of individual bonding elements that are confined to a relatively small area of the bottom of a package. In particular, the semiconductor module comprises a bonding interconnect structure configured to connect an integrated package to a printed circuit board (PCB), wherein the integrated antenna structures are located at greater center-to-center distance from the IC device than the three dimensional interconnect structures. Therefore, the bonding interconnect structures are confined to a connection area that causes a part of the package containing the one or more antenna structures to extend beyond the bonding interconnect structure as a cantilevered structure. Such a bonding interconnect structure result in a package that is in contact with a PCB at a relatively small area that supports the load of the package.

One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.

Process for the simultaneous deposition of crystalline and amorphous layers with doping

A device includes a semiconductor chip with a ring-shaped metal structure extending along the contour of a first main surface of the semiconductor chip. An encapsulation body encapsulates the semiconductor chip and defines a second main surface. An array of external contact pads attaches to the second main surface of the encapsulation body, and at least one external contact pad of the array of external contact pads electrically couples to the ring-shaped metal structure.

Device including a ring-shaped metal structure and method

A fuse structure includes a substrate, a fuse conductive trace disposed closer to a first chip surface than to a second chip surface facing away from the first chip surface, a metallization layer on the substrate disposed on a side of the fuse conductive trace facing away from the first chip surface, and a planar barrier multilayer assembly disposed between the fuse conductive trace and the metallization layer and including multiple barrier layers of different materials, wherein the fuse conductive trace, the metallization layer and the barrier multilayer assembly are arranged such that when cutting the fuse conductive trace and the barrier multilayer assembly, a first area of the metallization layer is electrically isolated from a second area of the metallization layer.

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Munich, Germany

Josef Boeck