Massana Research Limited

Aspire Technology LLC

Jose Rodriguez

Brian Paul Murray

Vincent Berg

Brian Mccormack

Christopher Bleakley

Pedro Pimentel

The present invention relates to a system and method for calculating spare capacity in a Fixed Wireless Access (FWA) communication network at sector and network level. The capacity is measured in terms of sellable customers, that is, the number of Customer Premises Equipment (CPEs) that can be connected to a sector in order to deliver a minimum guaranteed downlink speed at a busy hour to each user. Using the available technical assets, business requirements (installation metrics, guaranteed speed, sales rate, CPE categories) and the performance of each individual sector and customer (cell and user delivered throughputs, radio quality of existing customers, activity ratio of existing customers), the present invention enables accurate estimation of the remaining number of sellable customer premise equipment, and to identify capacity bottlenecks, forecast capacity expansions and plan marketing campaigns or promotions. In addition, the invention provides the ability to identify sectors with no spare capacity and provides inferences on the reasons for the no spare capacity state. The system as per the present invention comprises a computing unit having a comparison unit and a user interface for enabling the afore-mentioned method.

System and method for calculating and managing maximum number of sellable customer premise equipment in a fixed wireless access communication network

An address generation unit (AGU) and a digital signal processor (DSP) including such an AGU are disclosed. The AGU ( ) has a register file ( ) providing order (R), stage (S), and displacement (N) values to a digital addressing unit (DAU) ( ) for performing one of eight addressing operations. The register file provides an input (X) to the DAU and receives an output (Y) from the DAU. Within the DAU ( ), selection multiplexers ( ) select full adder outputs to provide Y, or bit-select from adders and the input (X) to provide Y. For a radix- operation, most significant bits (MSBs) are taken from the input (X), middle bits are taken from the output of a first adder (adder ), and the least significant bits (LSBs) are taken from the output of a second adder (adder ) if there is a carry out from the first adder. The AGU may also include bit reverse blocks connected at both the input and output of an adder. The DSP includes a program control unit for delivering a control signal to the AGU for selection of a required addressing operation.

Address generation unit and digital signal processor (DSP) including a digital addressing unit for performing selected addressing operations

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Dublin, Ireland

Jose Rodriguez