International Business Machines Corporation

Globalfoundries Inc.

Jose R Brunheroto

Frank Andre Schaffa

Julio Nogima

Frans Laemen

William J Anzick

Charles Ray Johns

Valentina Salapura

Martin Ohmacht

Chen-Yong Cher

Michael K Gschwind

Dong Chen

Paul William Coteus

Michael A Blocksome

Alan G Gara

James Allan Kahle

Joseph D Ratterman

Philip Heidelberger

Adam James Muff

Todd Edward Takken

Bruce Martin Fleischer

Alexandre E Eichenberger

Robert William Wisniewski

Thomas M Gooding

John A Gunnels

Mark Edwin Giampapa

Burkhard Steinmacher-Burow

Kathryn Mary O'Brien

Mark Gregory Megerian

Matthias Augustin Blumrich

Sameh W Asaad

Shawn Anthony Hall

John Kevin O'Brien

Thomas Winters Fox

Barry Marshall Trager

Peng Wu

Charles David Wait

Sameer Kumar

James Anthony Marcella

Todd Alan Inglett

George L Chiu

Krishnan Sugavanam

Gerard Vincent Kopcsay

Jeffrey John Parker

Robert Matthew Senger

Noel A Eisley

Craig Brian Stunkel

Rudolf Adriaan Haring

David L Satterfield

Douglas R Miller

Amith R Mamidala

Yutaka Sugawara

Kristan D Davis

Michael B Mundy

Matthew Roger Ellavsky

Abdullah Kayi

Robert E Walkup

Changhoan Kim

James Lee Van Oosten

Samuel J Miller

Constantinos Evangelinos

Ruth Janine Poole

Gabor J Dozsa

Peter Boyle

Brant L Knudson

Ralph E Bellofatto

Norman Christ

Kahn C Evans

Nelson Mimura Gonzalez

William Maupin Stockdell

Fausto Artico

Alfred Thomas Watson, Iii

Patrick D Siegl

Juan Gonzalez Garcia

Brian E Smith

Hubertus Franke

Ravi Nair

Eric Hsiao

Peter S Lee

James C Sexton

Alessandro Morari

Jamin Naghmouchi

An approach is disclosed that identifies a home node of a data granule. The process is performed by an information handling system (a local node) that retrieves a global virtual address directory. The global virtual address directory maps shared virtual addresses to a number nodes that includes the local node with one of the nodes being the home node. The shared virtual addresses correspond to a plurality of memory addresses that are stored in a shared virtual memory that is shared amongst the plurality of nodes. The approach receives a selected shared virtual address, retrieves, from the global virtual address directory, the home node associated with the selected shared virtual address, and accesses the data granule corresponding to the selected shared virtual address from the home node.

Identifying location of data granules in global virtual address space

An approach is disclosed that maintains a consistent view of a virtual address by a local node which writes a first value to the virtual address and, after writing the first value, establishes a snapshot consistency state of the virtual address. The virtual address is shared amongst any number of processes and the processes includes a writing process and other processes that read from the virtual address. After writing the first value, the writing process writes a second value to the virtual address. Even after writing the second value, the first value is still visible to the other processes.

Global virtual address space consistency model

An approach is disclosed that caches distant memories within the storage a local node. The approach provides a memory caching infrastructure that supports virtual addressing by utilizing memory in the local node as a cache of distant memories for data granules. The data granules are accessed along with metadata and an ECC associated with the data granule. The metadata is updated to indicate storage of the selected data granule in the cache.

Caching data from remote memories

An approach is described that accesses data in a shared memory that is shared amongst nodes that include a local node and remote nodes. The local node receives a name corresponding to a named data element in a Coordination Namespace, the Coordination Namespace having been created in a memory distributed amongst the nodes. A hash function is applied to at least a portion of the name with a result of the hash function being a natural node indicator. Data corresponding to the named data element is requested from a natural node identified by the indicator. Based on the request, a response is received from the natural node.

Coordination namespace processing

Methods for dynamically executing computer code across multiple disparate processing unit architectures are disclosed. During execution of a first portion of computer code on a first processing unit, it is determined that a first dynamic hardware behavior of a plurality of dynamic hardware behaviors will occur at a subsequent point in time, based on a second dynamic hardware behavior that is occurring. The methods include determining to execute code corresponding to the first dynamic hardware behavior on a second processing unit, rather than the first processing unit, and scheduling computer program code corresponding to the first dynamic hardware behavior to execute on the second processing unit rather than the first processing unit. Upon completion of execution of the computer code corresponding to the first dynamic hardware behavior, a remaining portion of the computer code is scheduled to execute on the first processing unit.

On-the fly scheduling of execution of dynamic hardware behaviors

Methods for estimating accelerator performance for dynamic hardware behaviors are disclosed. Computer program code to be executed on a first processing unit is received, and an execution of the computer code on the first processing unit is monitored to determine a plurality of performance characteristics. A plurality of dynamic hardware behaviors is determined by applying a clustering algorithm to the performance characteristics, and an equivalent accelerator portion of computer code to be executed on a second processing unit is generated by translating a set of instructions in a first portion of computer code corresponding to a first one of the plurality of dynamic hardware behaviors to an equivalent set of instructions to be executed on the second processing unit. An estimated measure of performance for executing the equivalent accelerator portion on the second processing unit is determined for the first one of the plurality of dynamic hardware behaviors.

Processing unit performance projection using dynamic hardware behaviors

A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.

Multi-petascale highly efficient parallel supercomputer

There is provided a processor implemented method for controlling a lock-stepped cohort. The method includes receiving instructions for each of a first lane and a second lane. The first lane is for the lock-stepped cohort and the second lane is for another cohort. The method further includes detecting a condition in which a first instruction at the first lane will have a higher latency than a second instruction at the second lane. The method also includes setting an indicator indicating where the first lane encountered the first instruction. The method additionally includes setting the first lane to inactive, while keeping the second lane active. The method further includes setting the first lane to active on a subsequent opportunity to execute said first instruction.

Load synchronization with streaming thread cohorts

A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.

Disclosed are a method and apparatus for replacing pre-fetched data in a pre-fetch cache. In one embodiment, each line of the pre-fetch cache will be accessed at most M times. A line accessed M times can be evicted from the cache without any performance loss. In this embodiment, a counter is added to each pre-fetch data line to track how many times it has been accessed. In another embodiment, a displacement bit is added to each pre-fetch data line, and when a defined portion of the data line is accessed, this bit is set to a given value, indicating that the line can be evicted.

Method and apparatus for efficient replacement algorithm for pre-fetcher oriented data cache

Method and system aspects provide for automated monitoring of quality of service of digital video material being distributed and played. The aspects include embedding a signature in each frame of the digital video material by a program source device control. Computation of play-out statistics for the digital video material based on the signature by a program play-out device control is also included.

Method and system for automated monitoring of quality of service of digital video material distribution and play-out

A system and method for a seamless splicing/spot insertion strategy for MPEG-2 digital video/audio transport stream with no previously encoded information. This strategy, considering the time dependency between MPEG-2 frames, results in a new stream with smooth transition from a main stream to a spot stream without any encoded mark increasing possibilities for utilization of MPEG-2 contents. This strategy further facilitates local and remote switching (like local advertisement insertion) and produces successful decoding and presentation of all MPEG-2 packets around the splicing point. It takes into account several kinds of MPEG-2 related discontinuities: transport header continuity counter gaps, temporal reference discontinuity for frame presentation and PCR/PTS/DTS discontinuities.

Seamless splicing/spot-insertion for MPEG-2 digital video/audio stream

A system and method for demultiplexing a TDM channel by redirecting all transport packets communicated on said channel as containing one of a multitude of possible PIDs, while recreating the CBR of the original transport packet transmission by restoring all discarded IDLE packets to enable time delayed re-transmission utilizing a generic TDM function.

Method and apparatus for demultiplexing a shared data channel into a multitude of separate data streams, restoring the original CBR

Transport packet multiplexing system and methodology that provides accurate bandwidth control, allowing bandwidth requirements to vary per multiplexed data stream while guaranteeing bandwidth availability. Accurate timing control is provided by implementing a real-time scheduling mechanism for adjusting the timing information based upon timing information obtained at the time of multiplexing to accurately represent environmental changes.

Method and apparatus for multiplexing a multitude of separate data streams into one shared data channel, while maintaining CBR requirements

A system and method for enabling real-time searching of patterns over a shared media including the capability of simultaneously searching multiple logical streams over the shared media. Patterns found are reported to the host system using some pre-assigned messages. One particular application of this invention is to search an MPEG-2 program stream, indicating the points (e.g., start-codes) where a new picture starts.

System and method for searching patterns in real-time over a shared media

Growing community of inventors

Mohegan Lake, NY, United States of America

Jose R Brunheroto