Nxp Usa, Inc.

Freescale Semiconductor,inc.

Jose Luis Suarez

Audel Sanchez

Michele Lynn Miera

Jenn Hwa Huang

Robert A Pryor

Eduard Jan Pabst

Yun Wei

Michael L Eleff

James Cotronakis

Flavio Hernandez Rodriguez

Gabriela Michel Sanchez

Interconnected substrate arrays, microelectronic packages, and methods for fabricating microelectronic packages for fabricating microelectronic packages utilizing interconnected substrate arrays containing integrated electrostatic discharge (ESD) protection grids are provided. In an embodiment, the method includes obtaining an interconnected substrate array having an integrated ESD protection grid. The ESD protection grid includes, in turn, ESD grid lines at least partially formed in singulation streets of an interconnected substrate array and electrically coupling die attachment regions of the substrate array to one or more peripheral machine ground contacts. Array-level fabrication steps are performed to produce an interconnected package array utilizing the interconnected substrate array, while electrically coupling the die attachment regions to electrical ground through the ESD protection grid during at least one of the array-level fabrication steps. Afterwards, the interconnected package array is singulated to yield a plurality of singulated microelectronic packages.

Interconnected substrate arrays containing electrostatic discharge protection grids and associated microelectronic packages

A die crack detector and method are provided. A first metal trace is formed over a substrate with the first metal trace configured to extend around a perimeter of a semiconductor die. A second metal trace is formed over the first metal trace with the second metal trace configured to overlap the first metal trace. A dielectric material is disposed between the first and second metal traces. A first detector terminal is coupled to the first metal trace and a second detector terminal coupled to the second metal trace. The detector terminals are configured to receive a predetermined voltage.

Die crack detector and method therefor

Methods and systems for achieving semiconductor-based circuits or systems having multiple components with one or more matched or similar characteristics or features are disclosed herein. In one example embodiment, a system includes a processing device that includes first, second, and third circuitry. The first circuitry is configured to generate control signals that at least indirectly cause a pick and place head mechanism to attempt to pick up and place at least some of first and second dice. The second circuitry is configured to assess whether attempts to implement one or more of first and second dice should be skipped based upon wafer map information. Further, the third circuitry is configured to determine whether a second position of a first one of the second dice is sufficiently proximate to a first position so that it would be appropriate to implement the first one of the second dice.

Method and system for achieving semiconductor-based circuits or systems having multiple components with one or more matched or similar characteristics or features

The embodiments described herein provide a die crack detector and method that use a conductive trace arranged to at least substantially extend around a perimeter of an integrated circuit die. A one-time programmable element, such as a fuse, is coupled in series with the conductive trace, and a package lead is electrically coupled to both the fuse and another operational element on the integrated circuit die. With the fuse intact the package lead can thus be used to determine a measurement of the conductivity of the conductive trace, with the measurement of conductivity indicative of the presence of a crack on the die. After such testing the fuse can be electrically opened, and the package lead used for normal operation of the device on the packaged die without the conductive trace interfering with this operation.

Die crack detector with integrated one-time programmable element

Systems and methods for releasing semiconductor dies from an adhesive tape or film. In some embodiments, a semiconductor manufacturing device may include: a chuck plate configured to support an array of semiconductor dies, where each die in the array has a top surface and a bottom surface, where each die's bottom surface is bonded to an adhesive tape, and where the chuck plate comprises one or more channels configured to apply a negative pressure to the adhesive tape; and a tape release element having an irregular surface, the tape release element disposed between the chuck plate and the adhesive tape.

Tape release systems and methods for semiconductor dies

An electronic apparatus includes a semiconductor substrate, a device structure supported by the semiconductor substrate, and a guard ring surrounding the device structure. The guard ring includes a plurality of conductive structures spaced apart from one another, supported by the semiconductor substrate, and coupled to a voltage source to establish an operating voltage for the guard ring.

Growing community of inventors

Chandler, AZ, United States of America

Jose Luis Suarez