International Business Machines Corporation

Jose Luis Pontes Correia Neves

Patrick James Meaney

Charles Jay Alpert

John Maxwell Cohn

Christopher J Berry

Paul Steven Zuchowski

Stephen Thomas Quay

Adam P Matheny

Lawrence D Curley

Gerald Strevig, Iii

Rama Gopal Gandham

William J Scarpero, Jr

Christopher Carney

Alice Hwajin Lee

Travis Wellington Pouarz

Biagio Pluchino

Examples described herein provide a computer-implemented method that includes identifying, by a processing device, a victim/aggressor pair of nets for an integrated circuit. The method further includes severing nets of the victim/aggressor pair of nets. The method further includes swapping severed segments of the nets. The method further includes rerouting the nets subsequent to swapping the severed segments of the nets.

Noise impact on function (NIOF) reduction for integrated circuit design

The process of laying out a floorplan for a clock control distribution network in an integrated chip design is simplified and the efficiency of a staging network created is improved. Rather than manually create the staging network in HDL or as a network description table while looking at a picture of the chip floorplan in a Cadence Viewer, an automated method which runs in the Cadence environment uses an algorithmic approach to the problem of maximizing the utilization of staging latches, eliminating unnecessary power and area usage. Efficiency is maximized by updating the Physical Layout directly with the staging solution arrived at by the algorithm.

Method of automating creation of a clock control distribution network in an integrated circuit floorplan

A system for improving a logic circuit may include a processor, and a logic circuit analyzer in communication with the processor to model a plurality of nets. The system may also include an interface in communication with the logic circuit analyzer to select a target slack-value for each one of the plurality of nets. The logic circuit analyzer may determine a slack-value for each net. In addition, the logic circuit analyzer may selectively reduce resistive-capacitive delay for each net respectively if the determined slack-value is less than the target slack-value for each respective net.

System for improving a logic circuit and associated methods

A method for reducing the effect of signal skew degradation in the design of an integrated circuit is provided. First, a circuit design library is created describing library cells as a function of one or more environmental variable, wherein the one or more environmental variable includes a skew degradation variable indicating skew degradation of a signal as a function of a total number of signal switches of the signal. Then, the integrated circuit design is modeled utilizing the circuit design library to determine a first skew degradation for each of the first and second signals at a first predetermined number of signal switches, and a second skew degradation for each of the first and second signals for a second predetermined number of signal switches, and further to determine a first relative skew degradation for a first predetermined number of signal switches and a second relative skew degradation for a second predetermined number of signal switches, wherein a relative skew degradation is equal to the difference of the skew degradation of the first signal and the skew degradation of the second signal for a given number of signal switches. Next, a skew shift equal to the difference between the first relative skew degradation and the second relative skew degradation is calculated. Finally, the integrated circuit design is modified such that a skew degradation of the first signal at the first predetermined number of signal switches is determined to be equal to the first skew degradation of the first signal minus half of the skew shift.

Method for reducing design effect of wearout mechanisms on signal skew in integrated circuit design

An apparatus and method for buffer selection for use in buffer insertion is provided. An optimal buffer library generator module operates to reduce a general buffer library down to a optimal buffer library based on parameters that are input to the optimal buffer library generator module. Based on these parameters, the optimal buffer library generator module selects buffers from the general buffer library for inclusion in an optimal buffer library. In a preferred embodiment, the optimal buffer library is generated by generating a set of superior buffers and inverters and clustering the set of superior buffers. A single buffer is then selected from each cluster for inclusion in the optimal buffer library. The result is a smaller buffer library which will provide approximately the same performance during buffer insertion while reducing the amount of computing time and memory requirements.

Apparatus and method for buffer library selection for use in buffer insertion

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Poughkeepsie, NY, United States of America

Jose Luis Pontes Correia Neves