International Business Machines Corporation

Globalfoundries Inc.

Jose Luis Neves

Adam P Matheny

James J Curtin

Douglas S Search

Christopher J Berry

Rajesh Ramkrishna Bordawekar

Alice Hwajin Lee

Kerim Kalafala

Sourav Saha

Michael H Wood

Thomas William Conti

Paul David Kartschoke

Michael J Cadigan, Jr

Haifeng Qian

Gregory M Schaeffer

Charlie Chornglii Hwang

Jesse Peter Surprise

Kaustav Guha

Tsz-mei Ko

Ray Raphy

Ravichander Ledalla

Chris Aaron Cavitt

Stephen C Warren

Christopher Harding

Edward J Hughes

Charles Jay Alpert

Phillip John Restle

Stephen Thomas Quay

Jiang Hu

Jonathan Yang Chen

William E Dougherty, Jr

Rama Gopal Gandham

Kevin M McIlvain

Rick L Dennis

Kevin M Mcllvain

Methods, systems and computer program products for determining recommended parameters for use in generating a word embedding model are provided. Aspects include storing a plurality of meaningful test cases. Each meaningful test case includes a test data profile and one or more test model parameters used to create a word embedding model that has been classified as yielding meaningful results. Aspects include receiving a production data set to be used in generating a new word embedding model. The production data set includes data stored in a relational database having a plurality of columns and a plurality of rows. Aspects include generating a data profile associated with the production data set. Aspects include generating a recommendation for one or more production model parameters for use in building a word embedding model based on the data profile associated with the production data set and the plurality of meaningful test cases.

Word embedding model parameter advisor

From a first attribute-value pair in a record, new data is created including a first token. Using a first model and using a processor and a memory, each token is vectorized into new data including a corresponding vector. From the record, a target row is selected, wherein a target attribute-value pair in the target row includes a value for which a semantic similarity computation is to be performed. Using a similarity measure, a set of most similar rows to the target row is determined, wherein each row in the set of most similar rows to the target row has a corresponding similarity measure above a threshold similarity measure and wherein each row in the set of most similar rows includes the target attribute. The set of most similar rows is used to compute a response to a database query.

Query response using semantically similar database records

Methods, systems and computer program products for updating a word embedding model are provided. Aspects include receiving a first data set comprising a relational database having a plurality of words. Aspects also include generating a word embedding model comprising a plurality of word vectors by training a neural network using unsupervised machine learning based on the first data set. Each word vector of the plurality of word vector corresponds to a unique word of the plurality of words. Aspects also include storing the plurality of word vectors and a representation of a hidden layer of the neural network. Aspects also include receiving a second data set comprising data that has been added to the relational database. Aspects also include updating the word embedding model based on the second data set and the stored representation of the hidden layer of the neural network.

Dynamic updating of a word embedding model

Techniques for noise impact on function (NIOF) reduction for an integrated circuit (IC) design are described herein. An aspect includes receiving a list of victim nets in which NIOF failures are present in an IC design. Another aspect includes attempting NIOF correction in each victim net of the list of victim nets. Another aspect includes, based on a failure of a NIOF correction in at least one victim net of the list of victim nets, saving the at least one victim net to a wire promote/demote list. Another aspect includes updating the list of victim nets based on the NIOF correction. Another aspect includes, based on determining that the updated list of victim nets is empty, promoting or demoting the at least one victim net from the wire promote/demote list in the IC design.

Noise impact on function (NIOF) reduction for integrated circuit design

Techniques for net routing for an integrated circuit (IC) design are described herein. An aspect includes receiving a netlist corresponding to a net in an IC design. Another aspect includes identifying intermediate logic in the net, wherein the intermediate logic is connected between a source and a sink of the net, and wherein the sink is located downstream from the source in the IC design. Another aspect includes hiding the intermediate logic from the netlist. Another aspect includes creating a global route in the IC design between the source and the sink of the net without the intermediate logic. Another aspect includes restoring the intermediate logic to the netlist. Another aspect includes placing the intermediate logic along the global route.

Net routing for integrated circuit (IC) design

Techniques for logic partition reporting for an integrated circuit (IC) design are described herein. An aspect includes generating a physical domain representation of an IC design based on a logic domain representation that includes a plurality of logic partitions, the physical domain representation including a plurality of logic clusters, each corresponding to a respective logic partition. Another aspect includes assigning a logic partition identifier corresponding to a logic partition of the plurality of logic partitions to each IC element in the physical domain representation. Another aspect includes assigning a pin name to each of the plurality of pins corresponding to the plurality of IC elements, wherein a pin name is derived based on the logic partition identifier of the IC element associated with the pin. Another aspect includes generating a timing report for a logic cluster based on the logic partition identifiers and the pin names.

Logic partition reporting for integrated circuit design

Techniques for an IC design include placing latches between a source and one or more sinks in the IC design, and performing an iterative process for maximizing slack on one or more input nets and one or more output nets for each of the latches, minimizing an absolute difference of the slack. The IC design includes optimizing routing for the latches and placing a clock gating latch in the IC design designated to control a LCB of LCBs. The IC design includes placing LCB logic in the IC design to control a required number of the LCBs, and placing a local clock buffer controller in the IC design in proximity to the positions of the latches.

Single-bit latch optimization for integrated circuit (IC) design

Techniques for logic partition identifiers for an integrated circuit (IC) design are described herein. An aspect includes receiving a logic domain representation of an IC design comprising a plurality of logic partitions each comprising a respective plurality of IC elements. Another aspect includes generating a physical domain representation of the IC design based on the logic domain representation comprising a plurality of logic clusters each corresponding to a respective logic partition, wherein each of the plurality of logic clusters comprises a respective plurality of IC elements. Another aspect includes assigning a logic partition identifier to each IC element in the physical domain representation, wherein the logic partition identifier of an IC element corresponds to a logic partition. Another aspect includes determining timing information for a logic partition based on the logic partition identifiers of the plurality of IC elements of a logic cluster associated with the logic partition.

Logic partition identifiers for integrated circuit design

Techniques for latches include ordering latches by connectivity from a source to sinks. An iterative process is performed which includes selecting a selected latch in the connectivity, drawing a bounding box around the selected latch to encompass input nets and output nets, and using a two-dimensional optimizer to find a new placement location for selected latch by solving for optimization criteria. The optimization criteria includes maximizing slack on the input and output nets of the selected latch, minimizing an absolute difference of the slack between the input output nets, and identifying the new placement location within the bounding box that balances maximizing the slack on input and output nets versus minimizing the absolute difference of the slack between input nets and output nets. The current location of the selected latch is updated between the source and sinks to be the new placement location identified in the bounding box.

Multi-fanout latch placement optimization for integrated circuit (IC) design

Techniques for parallel power down processing of an integrated circuit (IC) design are described herein. An aspect includes receiving IC design information comprising a plurality of IC elements. Another aspect includes identifying a plurality of timing endpoints in the IC design information. Another aspect includes determining a plurality of nets, each net comprising a respective subset of the plurality of IC elements, based on the identified plurality of timing endpoints. Another aspect includes performing power down processing of net drivers in the plurality of nets, wherein the power down processing of at least a subset of the plurality of nets is performed in parallel.

Parallel power down processing of integrated circuit design

An incremental parasitic extraction system includes a noise analysis module configured to perform a first noise analysis on at least one first net with respect to at least one aggressor net. The incremental parasitic extraction system further includes an optimizer module and an extraction module. The optimizer module performs a first optimization activity on the at least one first net based on results of the first noise analysis. The optimizer module further generates a first invalidation list based on the first optimization activity, and a second invalidation list based on a type of the first optimization action so as to add the second invalidation list to the first invalidation list. The extraction module processes the first and second invalidation lists and performs an extraction and noise analysis process on the first and second invalidation lists so as to determine at least one new RC network and associated noise analysis results.

Incremental parasitic extraction for coupled timing and power optimization

A first open path in a microprocessor design is identified. At least one modification to a design of that first open path is simulated. An updated arrival time at a pin is calculated based on the simulated modification or modifications. An updated path time is then calculated based on the updated arrival time.

Simulation of modifications to microprocessor design

Embodiments relate to power down processing including control path power adjustment. An aspect includes receiving, by a power down engine, chip layout data corresponding to a chip design. Another aspect includes determining a confluence point of a data path and a control path in the chip layout data. Another aspect includes determining the presence of a positive slack window in the control path of the confluence point. Yet another aspect includes powering up the control path to reduce the positive slack window.

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Wappingers Falls, NY, United States of America

Jose Luis Neves