Texas Instruments Corporation

Jose Luis Flores

Lewis Nardini

Ramakrishnan Venkatasubramanian

Maria B H Gill

Anthony Martin Hill

Rama Venkatasubramanian

Michael C Gill

Shane Stelmach

Timothy David Anderson

Gary L Swoboda

Joseph R Zbiciak

Abhijeet Ashok Chachad

Manisha Agarwala

Raguram Damodaran

Gary A Cooper

Jason Lynn Peck

Amritpal Singh Mundra

Venkateswar Reddy Kowkutla

John M Johnsen

Anthony J Lell

Soman Purushotaman

David Matthew Thompson

Denis R Beaudoin

Devanathan Varadarajan

Francisco A Cano

Samuel Paul Visalli

Varun Singh

Rejitha Nair

Sureshkumar Govindaraj

Ritesh Dhirajlal Sojitra

Mayur Joshi

Ivan Santos

An adaptive voltage scaling technique includes using a temperature sensor arranged on a semiconductor die to determine a current die temperature of the semiconductor die, using a performance sensor arranged on a semiconductor die to determine a current performance metric of the semiconductor die, determining whether the current performance metric matches an expected performance metric based at least partially on the current die temperature and, if the current performance metric does not match the expected performance metric, indicate a performance sensor error, when a performance sensor error is indicated, determining an updated power supply voltage for correcting the performance sensor error, and causing a current power supply voltage supplied by a power supply voltage source of the semiconductor die to be changed to the updated power supply voltage.

Adaptive voltage scaling using temperature and performance sensors

An integrated circuit comprises a set of processor cores, wherein each processor core of the set of processor cores includes BIST logic circuitry and multiple memory blocks coupled to the BIST logic circuitry. Each processor core further includes multiple power control circuitry, where each power control circuitry of the multiple power control circuitry is coupled to a respective processor core of the set of processor cores, multiple isolation circuitry, where each isolation circuitry of the multiple isolation circuitry is coupled to a respective processor core of the set of processor cores, a built-in-self repair (BISR) controller coupled to the each of the set of processor cores, each of the multiple power control circuitry, and each of the multiple isolation circuitry, and a safety controller coupled to the BISR controller, the multiple power control circuitry, and to the multiple isolation circuitry.

Distributed mechanism for fine-grained test power control

Circuits, systems and methods are provided. A circuit includes a subsystem, an interface, and a debugger. The interface includes power processing and management (PPM) circuitry coupled to the subsystem, and arbitration logic coupled to the PPM circuitry. In operation, the debugger issues a debug request to the arbitration logic to perform a debug operation on the subsystem, and, in response to the debug request, the arbitration logic provides an interrupt associated with the subsystem to the PPM circuitry. The PPM circuitry, in response to the interrupt and a determination that the subsystem is OFF, powers on the subsystem and provides a notification to the arbitration logic indicating that the subsystem is ON. The PPM circuitry also receives a notification from the arbitration logic that the debug operation related to the debug request is complete, and powers off the subsystem in response to that notification.

Integrated circuit with debugger and arbitration interface

An integrated circuit includes: a debugger; and an interface coupled to the debugger. The interface has: arbitration logic coupled to the debugger; a power processor coupled to the arbitration logic; and a power management network coupled to the power processor. The integrated circuit also includes subsystems coupled to the interface. The debugger is configured to perform debugging operations of the subsystems via the interface.

In described examples, an SoC includes at least two voltage domains interconnected with a communication bus. Detection logic in a first voltage domain determines when a voltage error occurs in a second voltage domain and isolates communication via the communication bus when a voltage error or a timing error is detected.

Electrical and logic isolation for systems on a chip

An integrated circuit includes: a clock domain having a clock domain input; and clock management logic coupled to the clock domain. The clock management logic includes: a PLL having a reference clock input and a PLL clock output; a divider having a divider input and a divider output, the divider input coupled to the PLL clock output; and bypass logic having a first clock input, a second clock input, a bypass control input, and a bypass logic output, the first clock input coupled to divider output, the second clock input coupled to the reference clock input, and the bypass logic output coupled to the clock domain input. The bypass logic selectively bypasses the PLL and divider responsive to a bypass control signal triggered by a reset signal. The reset signal also triggers a reset control signal delayed relative to the bypass control signal.

Integrated circuit with high-speed clock bypass before reset

In described examples, a latch includes active feedback circuitry for latching input information. A comparison of logic states between input and output states at selected times can determine whether, for example, the latch has correctly retained latch data. The latch can optionally be included within a scan chain, provide asynchronous latch error notifications, and/or synchronous notifications indicating where in the scan chain a latch error occurred.

Enhanced fault detection of latched data

An IC includes logic groups each including a launch and a capture FF with a logic cloud in between. A power switch is in series with a power supply node of the logic groups. The logic groups have a clock-gating and power control (PCGC) block for dynamically generating a power supply enable (PS_EN) signal output coupled to a control node of the power switch and a clock output (CLK_OUT) signal coupled to a clock input of the launch or capture FF for clocking the logic groups. The PCGC blocks receive an EN signal and a CLK_IN signal and dynamically generate the PS_EN signal and CLK_OUT signals. During clock cycles at least one logic group(s) does not contribute to an intended logic result for the IC the CLK_OUT signal disables switching of at least a portion of the logic group(s) while the PS_EN signal turns off power to the logic group(s).

Fine-grained dynamic power and clock-gating control

This invention is an electronic circuit with a low power retention mode. A single integrated circuit includes a circuit module and a droop switch circuit supplied by a voltage regulator. In a normal mode a PMOS source-drain channel connects the voltage regulator power to the circuit module power input or isolates them dependent upon a power switch input. In a low power mode a second PMOS connected between the first PMOS gate and output diode connects the first PMOS. This supplied the circuit module from the voltage regulator power as reduced in voltage by a diode forward bias drop. This lower voltage should be sufficient for flip-flops in the circuit module to retain their state while not guaranteeing logic operation. There may be a plurality of chain connected droop switch each powering a corresponding circuit module.

Power switch with source-bias mode for on-chip powerdomain supply drooping

A power supply for an electronic circuit enables a low effort retention mode. During a normal mode a circuit module is supplied a first voltage sufficient for a controlled circuit to operate. During the low effort retention mode the circuit module is supplied with a second voltage lower than the first voltage. The second voltage is sufficient for flop-flops to retain their state but not sufficient to guarantee proper circuit operation. The second voltage is produced by a voltage drop (droop) from the first voltage. The preferred embodiment includes a System On Chip and one external voltage regulator and an on-chip droop circuit for each circuit module.

On-chip power-domain supply drooping for low voltage idle/standby management

An embedded megamodule and an embedded CPU enable power-saving through a combination of hardware and software. The CPU configures the power-down controller (PDC) logic within megamodule and can software trigger a low-power state of logic modules during processor IDLE periods. To wake from this power-down state, a system event is asserted to the CPU through the module interrupt controller. Thus the entry into a low-power state is software-driven during periods of inactivity and power restoration is on system activity that demands the attention of the CPU.

Distributed power control for controlling power consumption based on detected activity of logic blocks

Traditionally, designs have been very conservative on power grid design using higher margins than those needed for safe operation. This is especially true for process driver designs which may not have enough data on process characteristics. This invention allows us to recoup these inefficiencies and to speed up the power up/power down dynamically. This invention sequences plural power supply switches serially or in plural parallel sets as set by a wake up mode.

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Richardson, TX, United States of America

Jose Luis Flores