International Business Machines Corporation

Jose L P Neves

Zhuo Li

Charles Jay Alpert

Stephen Thomas Quay

Robert Mahlon Averill, Iii

Chin Ngai Sze

John Maxwell Cohn

Yaoguang Wei

Eric Jason Fluhr

Tuhin Mahmud

Kerry Bernstein

Peter Anton Habitz

Scott Whitney Gould

Paul Steven Zuchowski

Larry Wissel

William F Smith

Mechanisms are provided for pruning a layer trait library for use in wire routing in an integrated circuit design process. The mechanisms receive a plurality of wirecodes and a metal stack definition. The mechanisms generate a verbose layer trait library based on all possible combinations of the wirecodes and layers of the metal stack definition. The mechanisms generate a pruned layer trait library by pruning the verbose layer trait library to remove redundant layer traits from the verbose layer trait library. In addition, the mechanisms store the pruned layer trait library for performing wire routing of an integrated circuit design.

Automatic generation of wire tag lists for a metal stack

Some example embodiments include a computer-implemented method for designing an integrated circuit. The computer-implemented method includes receiving a hierarchical network design for the integrated circuit, wherein the hierarchical design comprises a number of components that are coupled together. The computer-implemented method includes detecting that a component of the number of components has at least one of failed timing and incomplete timing based on a problem that comprises at least one of a missing assertion, one or more missing latches, a source driver having an input source slew that is greater than a source slew limit threshold, and a sink having an input sink slew that is greater than a sink slew limit threshold. The computer-implemented method includes replacing the component with a different component that is independent of the problem and testing others components of the number of components based on the different component.

Early design cycle optimization

Early design cycle optimzation

A method and a related program storage product for adding decoupling capacitance in an integrated circuit during the floor planning stage of the integrated circuit design. The invention overlay a power grid on the floor plan and then divides the power grid into regions or macros. For each region or macro, a support decoupling capacitance value required to support a voltage of the power grid and a native capacitance value are determined. Based on those values, a required decoupling capacitance value along with its decoupling capacitance area is determined. The design is then alternated based on the decoupling capacitance area.

Method for adding decoupling capacitance during integrated circuit design

A method of integrated circuit design using the selective replacement of increasingly noise tolerant cells is disclosed. The method involves compiling a library comprising a plurality of design element cells, sorting the library into groups of functionally-equivalent cells, and ordering the cells in each group from one extreme to the other extreme value of a featured parameter for which the integrated circuit is to be tested. Each one of the cells in the library have a known value of another parameter so that the substitution of a library cell for an original cell or another library cell does not affect the overall integrated circuit value for that known parameter. A substitution can thus be made with the knowledge that additional problems involving the known parameter are not being created. If a test of the integrated circuit discovers a problem in a particular cell's performance with regard to the featured parameter the appropriate library group is accessed and the failing cell is replaced with the first unused cell in the group. The process is repeated until the integrated circuit passes a performance test.

Method of integrated circuit design by selection of noise tolerant gates

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Poughkeepsie, NY, United States of America

Jose L P Neves