Advanced Micro Devices Corporation

Jose H Hernandez

Edward Hsia

Sayan Suanya

Darlene G Hamilton

In a semiconductor manufacturing process for manufacturing memory devices a method of screening hot temperature programmability rejects in memory devices during wafer sort at room temperature that would be rejected at class test at high temperature. All cells in the memory device are subjected to a first sequence of programming pulses at a voltage lower than the standard programming voltage. The number of pulses in the first sequence of programming pulses is from 1-5. Those die that verify as having been successfully programmed are passed. Those die that do not verify as having been programmed are subjected to a second sequence of programming pulses at a voltage lower than the standard programming voltage. The number of pulses in the second sequence of programming pulses is from 10 to 15 pulses. Those that verify as being programmed are marked as good and those that do not are repaired and retested.

Method of screening memory cells at room temperature that would be

In a semiconductor manufacturing process for manufacturing memory devices a method of screening hot temperature erase rejects in memory devices during wafer sort at room temperature that would be rejected at class test at high temperature. Selected cells of the memory device are subjected to a first sequence of erasure pulses at a high voltage until the selected cells are verified erased or until a first maximum number of erasure pulses has been reached, recording the number of pulses required to erase the selected cells, reading and repairing any defective memory cells, and subjecting all cells to a second sequence of erasure pulses until all cells are verified erased or until a maximum number of pulses has been reached wherein the second maximum number is a multiple of the recorded number.

Method of screening hot temperature erase rejects at room temperature

A method of testing Flash memory devices by performing wafer sort testing on main array cells and redundancy array cells of the Flash memory device and performing class testing on redundancy array cells only. There is a major savings of testing time with no decrease in quality of the final product.

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Milpitas, CA, United States of America

Jose H Hernandez