Arm Limited

Jose Gonzalez-Gonzalez

Alexander Alfred Hornung

Frederic Claude Marie Piry

Peter Richard Greenhalgh

Alex James Waugh

Adnan Khan

Gregory Andrew Chadwick

An apparatus comprises processing circuitry to issue demand memory access requests to access data stored in a memory system. Stride pattern detection circuitry detects whether a sequence of demand target addresses specified by the demand memory access requests includes two or more constant stride sequences of addresses interleaved within the sequence of demand target addresses. Each constant stride sequence comprises addresses separated by intervals of a constant stride value. Prefetch control circuitry controls issuing of prefetch load requests to prefetch data from the memory system. The prefetch load requests specify prefetch target addresses predicted based on the constant stride sequences detected by the stride pattern detection circuitry.

Prefetching based on detection of interleaved constant stride sequences of addresses within a sequence of demand target addresses

An apparatus () for processing data comprises a plurality of memory access request sources () which generate memory access requests. Each of the memory access request sources has a local memory (), and the apparatus also includes a shared memory (). When the memory access requests are atomic memory access requests, contention may arise over common data. When this occurs, the present technique triggers a switch of processing data in the local memory of a memory access request source to processing data in the shared memory.

Detection circuitry

Aspects of the present disclosure relate to an apparatus comprising decode circuitry to receive an instruction and identify the received instruction as a load instruction, and prediction circuitry to predict, based on a prediction scheme, a target address of the load instruction, and trigger a speculative memory access in respect of the predicted target address.

Methods and apparatus for handling processor load instructions

An apparatus and method of operating an apparatus are provided. The apparatus comprises execution circuitry to perform data processing operations specified by instructions and instruction retrieval circuitry to retrieve the instructions from memory, wherein the instructions comprise branch instructions. The instruction retrieval circuitry comprises branch target storage to store target instruction addresses for the branch instructions and branch target prefetch circuitry to prepopulate the branch target storage with predicted target instruction addresses for the branch instructions. An improved hit rate in the branch target storage may thereby be supported.

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Cambridge, United Kingdom

Jose Gonzalez-Gonzalez