Intel Corporation

Jose Gonzalez

Antonio Gonzalez

Grigorios Magklis

Julio Gago

Santiago Galan

Yen-Kuang Chen

Victor W Lee

Jatin Chhugani

Mikhail Smelyanskiy

Ganesh Suryanarayan Dasika

Changkyu Kim

Pedro Chaparro Monferrer

Pedro Chaparro

Victor Moya Del Barrio

Fernando Latorre

Qiong Cai

Gregory Martin Chrysler

Antonio González

Roger Espasa

Ryan N Rakvic

Fernando LaTorre

Some implementations disclosed herein provide techniques and arrangements for indicating a length of an instruction from an instruction set that has variable length instructions. A plurality of bytes that include an instruction may be read from an instruction cache based on a logical instruction pointer. A determination is made whether a first byte of the plurality of bytes identifies a length of the instruction. In response to detecting that the first byte of the plurality of bytes identifies the length of the instruction, the instruction is read from the plurality of bytes based on the length of the instruction.

Indicating a length of an instruction of a variable length instruction set

A region or group of pixels may be textured as a unit, using a range specifier and one or more anchor pixels to define the group. In some embodiments, processing grouped pixels improves efficiency.

Grouping pixels to be textured

A texture unit may be used to perform general purpose mathematical computations such as dot products. This enables some general purpose computations and operations to be offloaded from a central processing unit to the texture unit. The texture unit may use linear interpolators in order to perform the dot product calculations.

Texture unit for general purpose computing

A method and apparatus for scaling frequency and operating voltage of at least one clock domain of a microprocessor. More particularly, embodiments of the invention relate to techniques to divide a microprocessor into clock domains and control the frequency and operating voltage of each clock domain independently of the others.

Frequency and voltage scaling architecture

A device having multiple cores executes an algorithm to control Thin-Film Thermoelectric Coolers (TFTEC) that employ the Peltier effect to remove heat from the various cores of the multi-core processor. The algorithms may combine Thread Migration (TM) and Dynamic Voltage/Frequency Scaling (DVFS) to provide Dynamic Thermal Management (DTM) and TFTEC control.

Microarchitecture controller for thin-film thermoelectric cooling

A texture unit may be used utilized to perform general purpose mathematical computations such as dot products. This enables some general purpose computations and operations to be offloaded from a central processing unit to the texture unit. The texture unit may use linear interpolators in order to perform the dot product calculations.

A multithreaded clustered microarchitecture with dynamic back-end assignment is presented. A processing system may include a plurality of instruction caches and front-end units each to process an individual thread from a corresponding one of the instruction caches, a plurality of back-end units, and an interconnect network to couple the front-end and back-end units. A method may include measuring a performance metric of a back-end unit, comparing the measurement to a first value, and reassigning, or not, the back-end unit according to the comparison. Computer systems according to embodiments of the invention may include: a random access memory; a system bus; and a processor having a plurality of instruction caches, a plurality of front-end units each to process an individual thread from a corresponding one of the instruction caches; a plurality of back-end units; and an interconnect network coupled to the plurality of front-end units and the plurality of back-end units.

Multithreaded clustered microarchitecture with dynamic back-end assignment

An integrated circuit is cooled by microarchitecture controlled Peltier effect cooling. In one embodiment, a temperature sensor thermally coupled to at least a portion of the integrated circuit of a die is adapted to provide an output as a function of the temperature of an integrated circuit portion. Operation of a thermoelectric cooler thermally coupled to the integrated circuit portion is controlled as a function of the sensor output, wherein a controller of the integrated circuit controls the thermal electric cooler. Other embodiments are described and claimed.

Microarchitecture control for thermoelectric cooling

Methods and apparatus to provide leakage power estimation are described. In one embodiment, one or more sensed temperature values () and one or more voltage values () are utilized to determine the leakage power of an integrated circuit (IC) component. Other embodiments are also described.

Leakage power estimation

In one embodiment, the present invention includes a method for determining if data of a memory request by a first agent is in a memory region represented by a region indicator of a region table of the first agent, and transmitting a compressed address for the memory request to other agents of a system if the memory region is represented by the region indicator, otherwise transmitting a full address. Other embodiments are described and claimed.

Compressing address communications between processors

An apparatus associated with identifying a critical thread based on information gathered during meeting point processing is provided. One embodiment of the apparatus may include logic to selectively update meeting point counts for threads upon determining that they have arrived at a meeting point. The embodiment may also include logic to periodically identify which thread in a set of threads is a critical thread. The critical thread may be the slowest thread and criticality may be determined by examining meeting point counts. The embodiment may also include logic to selectively manipulate a configurable attribute of the critical thread and/or core upon which the critical thread will run.

Meeting point thread characterization

In some embodiments, an apparatus for an energy efficient clustered micro-architecture are disclosed. In one embodiment, the micro-architecture computes an energy delayproduct for each active instruction scheduler and one or more associated function blocks of a current architecture configuration over a predetermined period. Once the energy delayproduct is computed, the computed product is compared against an energy delayproduct calculated for a prior architecture configuration to determine an effectiveness (energy efficiency) of the current architecture configuration. Based on the effectiveness of the current architecture configuration, a number of active instruction schedulers and one or more associated functional blocks within the current architecture configuration is adjusted. In one embodiment, the number of active instruction schedulers and one or more associated functional blocks may be increased or decreased to improve power efficiency of the cluster micro-architecture. Other embodiments are described and claimed.

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Terrassa, Spain

Jose Gonzalez