Northrop Grumman Systems Corporation

Jose G Padilla

Roger S Tsai

Xianglin Zeng

Philip W Hon

Shih-En Shih

A three-dimensional wafer level packaged (WLP) integrated circuit that includes a pair of opposing circuit cells fabricated on separate wafers that have been bonded together to provide vertical circuit redundancy. The integrated circuits on each of the separate wafers are performance tested prior to the wafers being bonded together so as to designate good performing circuits as active circuit cells and poor performing circuits as inactive circuit cells. The inactive circuit cell for a particular pair of integrated circuits is metalized with a short circuiting metal layer to make it inoperable. The WLP integrated circuit implements a yield-enhancing circuit redundancy scheme on spatially uncorrelated wafers that avoids wasting valuable wafer x-y planar area, which provides cost savings as a result of more wafer area being available for distinct circuits on each wafer rather than sacrificed for traditional side-by-side redundant copies of circuits.

Yield enhancing vertical redundancy method for 3D wafer level packaged (WLP) integrated circuit systems

A coupled transmission line balun construction employs two pairs of planar interleaved spiral coils ( & ) formed on an electrically insulating or semi-insulating substrate ( ) defining a planar structure. One coil in each pair is connected in series to define the input transmission line of the balun, with one end ( ) of that transmission line being open circuit. The balun provides an ultra-wide bandwidth characteristic in the frequencies of interest for MMIC devices, is fabricated using the same techniques employed with fabrication of MMIC devices, and is of a physical size that lends itself to application within MMIC devices.

Growing community of inventors

South Gate, CA, United States of America

Jose G Padilla