International Business Machines Corporation

Globalfoundries Inc.

Jose Eduardo Moreira

Brian William Thompto

Kattamuri Ekanadham

Hung Qui Le

Pratap Chandra Pattnaik

Mauricio J Serrano

Manoj N Kumar

Jentje Leenstra

Michael K Gschwind

Lee Evan Eisen

Albert James Van Norstrand, Jr

Bruce Joseph Ronchetti

Jessica Hui-Chun Tseng

Dung Q Nguyen

Harold Wade Cain, Iii

David S Levitan

David Michael Daly

Jessica Tseng

Andreas Wagner

Balaram Sinharoy

Silvia Melitta Mueller

Joefon Jann

Ilie G Tanase

Hao Yu

William Pettit Horn

Markus Kaltenbach

Ramendra K Sahoo

Sam G Chu

Michael Huang

Manish Satyapal Gupta

Brett Olsson

Peng Wu

Vijay Krishnarao Naik

Gheorghe Almasi

Gianfranco Bilardi

Maja Vukovic

Hubertus Franke

Giles R Frazier

Jinho Hwang

Bruce Martin Fleischer

Maarten Jakob Boersma

Brian R Konigsburg

Nikolaos Anerousis

Kun Bai

Debapriya Chatterjee

Tejas S Karkhanis

Priya Ashok Nagpurkar

Adam J Oliner

Maged M Michael

Naresh Nayar

Randal Craig Swanberg

Joel Abraham Silberman

Sundeep Chadha

Richard James Eickemeyer

Phillip G Williams

Bradly George Frey

Sheldon Bernard Levenstein

Christian Zoellin

Cathy May

Patricia Maria Sagmeister

Myung Mun Bae

Fred Gehrung Gustavson

David Mui

Benjamin Herrenschmidt

Kaoutar El Maghraoui

Kalman Zvi Meth

Robert F Enenkel

Arnold Flores

Adnan M Agbaria

Il Park

David Joel Edelsohn

Sandhya Koteshwara

Samuel Pratt Midkiff

Douglas R G Logan

Manoj Kumar

A data ordering device includes a plurality of inputs N and a plurality of outputs M. There is a sorting network coupled between the plurality of inputs N and the plurality of outputs M. There are one or more latches comprising a buffer coupled between each input of the plurality of inputs N and a corresponding input of the sorting network. There are one or more latches comprising a buffer coupled between each output of the plurality of outputs M and a corresponding output of the sorting network. There is an input for a control signal operative to initiate a sorting of data between the plurality of inputs N and the plurality of outputs M. The data ordering device is coupled to a core of a central processing unit.

Reformatting matrices to improve computing efficiency

In response to encountering a function entry instruction while running an application, a processor computes an entry hash value using a hash of three hash input parameters, wherein one of the input parameters is a secret key stored in the special purpose register. In response to encountering a function exit instruction, the processor computes an exit hash value using the same three input parameters and the same hash used when computing the entry hash value. The processor determines if the entry hash value is the same as the exit hash value. In response to the entry hash value being the same as the exit hash value the processor exits the function and in response to the entry hash value not being the same as the exit hash value the processor executes a trap interrupt.

Comparing hash values computed at function entry and exit for increased security

A processor unit for multiply and accumulate ('MAC') operations is provided. The present invention may include the processor unit having a plurality of MAC units for performing a set of MAC operations. The present invention may include each MAC unit having an execution unit and a one-write one-read (“1W/1R”) register file, where the 1W/1R register file may have at least one accumulator. The present invention may include the execution unit of each MAC unit being configured to perform a subset of MAC operations by computing a product of a set of values received from another register file of the processor unit and adding the computed product to the at least one accumulator. The present invention may include each MAC unit being configured to perform the respective subset of MAC operations in a single clock cycle.

Dispatching multiply and accumulate operations based on accumulator register index number

Aspects of the present disclosure relate to encrypted data processing (EDAP). Encrypted data from a cache to be loaded into a register file can be accessed. The encrypted data can be decrypted to receive cleartext data. The cleartext data can be written to the register file. The cleartext data can be processed using at least one functional unit to receive cleartext computation results. The cleartext computation results can then be written back to the register file.

Encrypted data processing design including cleartext register files

A computer system, processor, computer program product, and method for executing instructions in a software application that includes a processor that can be dynamically controlled, in response to a value set in a control register, to operate in either a secure mode or a performance mode. In the secure mode, the processor: upon encountering a secure mode entry instruction, computes an entry hash value using a hash function and stores the entry hash value; and upon encountering a secure mode exit instruction, computes an exit hash value, loads the entry hash value, and determines whether the entry hash value is the same as the exit hash value, and depending upon verification of the hash values can execute the return function or transfer control to the operating system. In the performance mode, the processor: executes both the secure mode entry instruction and the secure mode exit instruction as no-operations.

Method and system for on demand control of hardware support for software pointer authentification in a computing system

A system may determine that two instructions may be combined based on a processing power of the processor and a size of the instructions, fuse the two instructions into a pair, map the two instructions with a single register tag, write the register tag into a mapper with bits indicating that the register tag is for a first instruction of the two instructions, write the register tag into the mapper with bits indicating that the register tag is for a second instruction of the two instructions, write the fused instruction pair into an issue queue, issue the fused instruction pair to a vector-scalar transformation units (VSU), and execute the two instructions.

Loosely-coupled slice target file data

Aspects of the present disclosure relate to encrypted data processing (EDAP). A processor includes a register file configured to store ciphertext data, an instruction fetch and decode unit configured to fetch and decode instructions, and a functional unit configured to process the stored ciphertext data. The functional unit further includes a decryption module configured to decrypt ciphertext data from the register file to receive cleartext data using an encryption key stored within the functional unit. The functional unit further includes a local buffer configured to store the cleartext data. The functional unit further includes an arithmetic logical unit configured to generate cleartext computation results using the cleartext data The functional unit further includes an encryption module configured to encrypt the cleartext computation results to generate ciphertext computation results for storage back into the register file.

Encrypted data processing design including local buffers

Embodiments for providing memory access operations for graph analytics by a processor are disclosed. An entire chunk of load and store instructions may be atomically and concurrently executed, where the entire chunk of the load and store instructions are delineated from a plurality of alternative load and store instructions.

Memory access operations for large graph analytics

Aspects include a compute array of a processor with mixed-precision numerical linear algebra support. A first precision and a first shape of a first input matrix and a second precision and a second shape of a second input matrix to the compute array are determined. A plurality of linear algebra operations is repeated in parallel within the compute array to update a result matrix in an accumulator register based on the first input matrix, the second input matrix, and a number of rank updates of the result matrix to store in the accumulator register.

Compute array of a processor with mixed-precision numerical linear algebra support

A computer system, processor, and method for processing information is disclosed that includes at least one computer processor; a main register file associated with the at least one processor, the main register file having a plurality of entries for storing data, one or more write ports to write data to the main register file entries, and one or more read ports to read data from the main register file entries; one or more execution units including a dense math execution unit; and at least one accumulator register file having a plurality of entries for storing data. The results of the dense math execution unit in an aspect are written to the accumulator register file, preferably to the same accumulator register file entry multiple times, and the data from the accumulator register file is written to the main register file.

Instruction handling for accumulation of register results in a microprocessor

A Reduced Instruction Set Computer ('RISC') supporting large-word operations in a computing environment is disclosed. In one implementation, in response to receiving one or more control signals from a central processing unit ('CPU'), a set of operations are executed on a state of a special purpose execution unit (&#x201c;SPU&#x201d;) having a plurality of SPU registers, the SPU being associated with the CPU and the state of the SPU having word widths of one or more of the plurality of registers being greater in size than word widths of a plurality of CPU registers of a computing system and a set of state-master bits to synchronize the state of the SPU and a state of the CPU. The results of the set of operations are stored in the plurality of CPU registers or an alternative set of the plurality of SPU registers.

Supporting large-word operations in a reduced instruction set computer ('RISC') processor

Method and systems for creating a sequence of fused instructions. An instruction stream is obtained, and a window of instructions from the instruction stream is examined and one or more groups of instructions that satisfy one or more fusion rules are identified. One or more of the groups of instructions that satisfy the one or more fusion rules are fused and a maximal length data dependence chain in the instruction stream is analyzed by analyzing every node in a dependence graph in a selected window of instructions. Fusion of an instruction group is prevented based on the maximal length data dependence chain.

Instruction fusion using dependence analysis

Methods and systems of matrix multiplication are described. In an example, a processor can multiply a first entry of a first vector of a first data array with a second vector of a second data array to generate a third vector of a third data array. The processor can store the third vector of the third data array in the second register file. The processor can multiply a second entry of the first vector with the second vector to generate a fourth vector of the third data array. The processor can store the fourth vector of the third data array in the second register file. The processor can combine vectors of the third data array that are stored in the second register file to produce the third data array.

Half-precision floating-point arrays at low overhead

Aspects include a compute array of a processor with mixed-precision numerical linear algebra support. A first precision and a first shape of a first input matrix and a second precision and a second shape of a second input matrix to the compute array are determined. A number of rank updates of a result matrix to store in an accumulator register having a predetermined size are determined, where the number of rank updates is based on the first precision and the first shape of the first input matrix, the second precision and the second shape of the second input matrix, and the predetermined size of the accumulator register. A plurality of linear algebra operations is repeated in parallel within the compute array to update the result matrix in the accumulator register based on the first input matrix, the second input matrix, and the number of rank updates.

Embodiments of the present invention are directed to a new instruction set extension and a method for providing 3D lane predication for matrix operations. In a non-limiting embodiment of the invention, a first input matrix having m rows and k columns and a second input matrix having k rows and n columns are received by a compute array of a processor. A three-dimensional predicate mask having an M-bit row mask, an N-bit column mask, and a K-bit rank mask is generated. A result matrix of up to m rows, up to n columns, and up to k rank updates is determined based on the first input matrix, the second input matrix, and the predicate mask.

Three-dimensional lane predication for matrix operations

Growing community of inventors

Irvington, NY, United States of America

Jose Eduardo Moreira