Kovio, Inc.

Cypress Semiconductor Corporation

Jose Arreola

Christopher S Gudeman

J Devin MacKenzie

J Montague Cleeves

Gabriel M Li

Shahin Sharifzadeh

K Nirmal Ratnakumar

Kenelm G D Murray

An EAS device, and methods for making the device for tuning the resonant frequency of the same is disclosed. The EAS device includes: an outer inductor having one end coupled to a linear or nonlinear capacitor plate; an inner inductor having one end coupled to the other type of capacitor; a first dielectric film on the outer and inner inductors and the capacitor plates coupled thereto, having openings exposing other ends of the outer and inner inductors; a second linear capacitor plate on the dielectric film; a second nonlinear capacitor plate on the dielectric film; a second dielectric film containing holes for the second linear and nonlinear capacitor plates, and exposing the other ends of the first and second inductors; and first and second conducting straps on the second dielectric film, configured to electrically connect one of the exposed inductor ends to a corresponding second capacitor plate.

Electronic article surveillance (EAS) tag/device with coplanar and/or multiple coil circuits, an EAS tag/device with two or more memory bits, and methods for tuning the resonant frequency of an RLC EAS tag/device

An electronic article surveillance (EAS) tag/device with coplanar and/or multiple coil circuits, a tag/device with two or more memory bits, and methods for making and tuning the resonant frequency of an EAS tag/device. The device generally includes: an outer inductor having one end coupled to a capacitor plate; an inner inductor having one end coupled to an other capacitor plate; a first dielectric film on the outer and inner inductors and the capacitor plates coupled thereto, having openings therein exposing other ends of the outer and inner inductors; a linear capacitor plate and a nonlinear capacitor plate on the first dielectric film; a second dielectric film containing holes therein for the second linear and nonlinear capacitor plates, and exposing the other ends of the first and second inductors; and first and second conducting straps on the second dielectric film, electrically connecting one of the exposed inductor ends to a corresponding second capacitor plate.

In an embodiment of an integrated circuit structure having buried layer substrate isolation and a method for forming same, a buried layer having conductivity type opposite to that of an overlying well region is used for wells containing transistors prone to noise generation, where the wells are of the same conductivity type as the substrate. The buried layer may in some embodiments include a first portion underlying the transistor and a second portion spaced apart from and laterally surrounding the first portion. In some embodiments, the circuit may include a doped annular region of the same conductivity type as the buried layer, where the annular region contacts a portion of the buried layer and laterally surrounds the transistor. The circuit may further include metallization adapted to connect the well and annular region to opposite polarities of a power supply voltage, or in some embodiments to preclude such connection.

Buried layer substrate isolation in integrated circuits

Growing community of inventors

Mountain View, CA, United States of America

Jose Arreola