Intel Corporation

Other

Jose Andy Vargas

Mohan J Kumar

Theodros Yigzaw

Sarathy Jayakumar

Akhilesh Kumar

Eric R Delano

Mani Ayyar

Ioannis T Schoinas

Michael Mishaeli

Ganapati Srinivasa

Julius Yuli Mandelblat

Hisham Shafi

Geeyarpuram N Santhanakrishnan

Zeev Sperber

Murugasamy K Nachimuthu

Prashant Sethi

Koichi Yamada

James B Crossland

Shlomo Raikin

Ehud Cohen

Randolph L Campbell

Jay Jayasimha

Joseph A Bennett

Suresh K Marisetty

Doddaballapur N Jayasimha

Michael A Rothman

Efraim Rotem

David J Harriman

Eliezer Weissmann

Krishnakanth Venkata Sistla

Paul S Diefenbaugh

Jasmin Ajanovic

Yen-Cheng Liu

Jeremy J Shrall

Guy M Therien

Ashok Raj

Shivnandan D Kaushik

Robert E Gough

Kai Cheng

Lihu Rappoport

Andrew J Fish

Mark Doran

Anil Aggarwal

Andrew D Henroid

Larisa Novakovsky

Clifford D Hall

Neelam Chandwani

Baskaran Ganesan

Oded Lempel

Chen Koren

Gautam Doshi

Cameron B McNairy

Scott D Brenden

William G Auld

Gopikrishna Jandhyala

Anthony E Luck

Jack Novak

Jim B Crossland

Stan Domen

Steve Pawlowski

Ioannis Yannis Schoinas

Alfonso Heras

Rajender Kuramkote

Alfredo Vargas

Douglas E Covelli

Douglas Covelli

An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.

Apparatus and method for detecting and recovering from data fetch errors

Described is a computing platform, which comprises: a non-volatile memory having a firmware boot program; and a CPU to execute the firmware boot program when the CPU is reset, the firmware boot program including instructions to create Power and Performance Measurement (PPM) interface data structures including an error injection table structure to provide error injection services to an OS.

Computing platform with interface based error injection

A system for processing biological specimens mounted on microscope slides by adding and removing processing fluids from microscope slides by means of capillary action using a slide holder capable of holding multiple microscope slides, and a spacer positioned in between two slides of a slide pair to create a capillary gap. A capillary gap adjuster can be used to pinch and release one end of the slide pair to create a pulsatile action to mix the reagent within the capillary gap. The system may further include a reagent holder, an absorbent pad, a series of reagent baths, and an incubator for holding one or more slide holders.

System and method for processing biological specimens

In some embodiments, a PPM interface may be provided with functionality to facilitate to an OS memory power state management for one or more memory nodes, regardless of a particular platform hardware configuration, as long as the platform hardware is in conformance with the PPM interface.

Computing platform interface with memory management

A vehicle driver exercising system includes a pair of hand exercising members each removably engaged with a steering wheel. The hand exercising members each include a clip having an inner surface and an outer surface. The clip receives the steering wheel and a base is attached to the outer surface. A housing is slidably mounted to an upper surface of the base and has an outer flange is movable between an extended position extended upwardly from and spaced away from the base or a collapsed position abutting the base. A biasing member is positioned in the base and biases the housing toward the extended position.

Vehicle driver exercising system

A processor includes a logic to determine an error condition reported in an error bank. The error bank is communicatively coupled to the processor and is associated with logical processors of the processor. The processor includes another logic to generate an interrupt indicating the error condition. The processor includes yet another logic to selectively send the interrupt to a single one of the logical processors associated with the error bank.

Instruction and logic for machine checking communication

A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.

Method, system, and apparatus for dynamic reconfiguration of resources

In some embodiments, a PPM interface may be provided with functionality to facilitate to an OS RAS services for one or more hardware components, regardless of a particular platform hardware configuration, as long as the platform hardware and OS are in conformance with the PPM interface.

Computing platform performance management with RAS services

An apparatus and method are described for detecting and correcting instruction fetch errors within a processor core. For example, in one embodiment, an instruction processing apparatus for detecting and recovering from instruction fetch errors comprises, the instruction processing apparatus performing the operations of: detecting an error associated with an instruction in response to an instruction fetch operation; and determining if the instruction is from a speculative access, wherein if the instruction is not from a speculative access, then responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core.

Apparatus and method for implement a multi-level memory hierarchy

Embodiments of apparatus, computer-implemented methods, systems, devices, and computer-readable media are described herein for a computing device with a platform entity such as an interrupt handier configured to notify an operating system or virtual machine monitor executing on the computing device of an input/output error-containment event. In various embodiments, the interrupt handler may be configured to facilitate recovery of a link to an input/output device that caused the input/output error-containment event, responsive to a directive from the operating system or virtual machine monitor.

Recovery after input/ouput error-containment events

Disclosed is an apparatus and a method to inject errors to a memory. In one embodiment, a dedicated interface includes an error injection system address register and an error injection mask register coupled to the error injection system address register. If the error injection system address register includes a system address that matches an incoming write address, the error injection mask register outputs an error to the memory.

Method and apparatus for injecting errors into memory

Various embodiments are described herein. Some embodiments include an Operating System and a platform. The platform includes a processor having an error register. The Operating System can write to the error register only via the platform in a secure manner (for example, using platform firmware). Other embodiments are described and claimed.

Secure error handling

Growing community of inventors

Rescue, CA, United States of America

Jose Andy Vargas