Intel Corporation

Jose-Alejandro Pineiro

Antonio Gonzalez

Jaume Abella

Xavier Vera

Amit Gradstein

Simon Rubanovich

Benny Eitan

Ravishankar Iyer

Ronny Ronen

Thomas D Fletcher

Donald K Newell

Fernando Latorre

Srihari Makineni

Javier Carretero Casado

Pedro Lopez

Jaideep Moses

Josep M Codina

Enric Gibert

Ramesh G Illikkal

A math circuit for computing an estimate of a transcendental function is described. A lookup table storage circuit has stored therein several groups of binary values, where each group of values represents a respective coefficient of a first polynomial that estimates the function to a high precision. A computing circuit uses a portion of a binary value, that is also taken from one of the groups of values, to evaluate a second polynomial that estimates the function to a low precision. Other embodiments are also described and claimed.

Math circuit for estimating a transcendental function

Apparatus and computing systems associated with cache sharing based thread control are described. One embodiment includes a memory to store a thread control instruction and a processor to execute the thread control instruction. The processor is coupled to the memory. The processor includes a first unit to dynamically determine a cache sharing behavior between threads in a multi-threaded computing system and a second unit to dynamically control the composition of a set of threads in the multi-threaded computing system. The composition of the set of threads is based, at least in part, on thread affinity as exhibited by cache-sharing behavior. The thread control instruction controls the operation of the first unit and the second unit.

Cache sharing based thread control

In one embodiment, the present invention includes a method for protecting a value to be stored in a register of a register file with a first level of protection if the value is predicted to be used for a first time period, and protecting the value with a second level of protection if the value is predicted to be used for a second time period. Other embodiments are described and claimed.

Selectively protecting a register file

In general, in one aspect, the disclosure describes an apparatus that includes a memory device having a plurality of memory cells. An inverter is used to invert data and tag information destined for the memory device. A register is used to capture the inverted data and tag information. A write inverted value logic is used to determine when to enable writing the inverted data and tag information from the register to the memory device. When inverted data and tag information is written to a memory cell the memory cell is invalidated.

Memory content inverting to minimize NTBI effects

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Barcelona, Spain

Jose-Alejandro Pineiro