Texas Instruments Corporation

Jose A Rodriguez-Latorre

Hugh Pryor McAdams

Manish Goel

Ning Tan

An apparatus with a burn-in board containing a microcontroller unit and a heater socket for insitu testing of a packaged integrated circuit while under stress. A method for insitu testing of a packaged integrated circuit while under stress. A method for insitu testing of multiple packaged integrated circuits while under stress.

Low cost apparatus for insitu testing of packaged integrated circuits during stressing

Disclosed embodiments include a memory device having a memory array that includes a first memory cell coupled to a first bit line and a second memory cell coupled to a second bit line and a sense amplifier that includes first and second transistors arranged in a cross-coupled configuration with third and fourth transistors, the first and second transistors being of a first conductivity type and the third and fourth transistors being of a second conductivity type, a first inverter having an input coupled to a first common drain terminal of the first and third transistors and an output coupled to the first bit line, and a second inverter having an input coupled to a second common drain terminal of the second and fourth transistors and an output coupled to the second bit line.

Circuit and method for imprint reduction in FRAM memories

A method of operating a memory circuit (FIGS.A andB) is disclosed. The method includes writing true data () to a plurality of bits (B, B). A first data state () is written to a signal bit (B) indicating the true data. The true data is read and complementary data () is written to the plurality of bits. A second data state () is written to the signal bit indicating the complementary data.

A method of operating a memory circuit (FIGS.A andB) is disclosed. The method includes writing true data (01) to a plurality of bits (B, B). A first data state (0) is written to a signal bit (B) indicating the true data. The true data is read and complementary data (10) is written to the plurality of bits. A second data state (1) is written to the signal bit indicating the complementary data.

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Dallas, TX, United States of America

Jose A Rodriguez-Latorre